vga.tan.rpt

VGA 测试程序

; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; k[0]                  ; k[0]                  ; clk        ; clk      ; None                        ; None                      ; 0.501 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; vs                    ; vs                    ; clk        ; clk      ; None                        ; None                      ; 0.501 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; vga_read_dispaly~reg0 ; vga_read_dispaly~reg0 ; clk        ; clk      ; None                        ; None                      ; 0.501 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; GRB[1]                ; GRB[1]                ; clk        ; clk      ; None                        ; None                      ; 0.501 ns                ;
+-------+------------------------------------------------+-----------------------+-----------------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+-------------------------------------------------------------------------------------------+
; tco                                                                                       ;
+-------+--------------+------------+-----------------------+------------------+------------+
; Slack ; Required tco ; Actual tco ; From                  ; To               ; From Clock ;
+-------+--------------+------------+-----------------------+------------------+------------+
; N/A   ; None         ; 12.750 ns  ; vs                    ; vga_vs_control   ; clk        ;
; N/A   ; None         ; 8.345 ns   ; hs                    ; vga_hs_control   ; clk        ;
; N/A   ; None         ; 7.632 ns   ; vga_read_dispaly~reg0 ; vga_read_dispaly ; clk        ;
+-------+--------------+------------+-----------------------+------------------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 6.1 Build 201 11/27/2006 SJ Full Version
    Info: Processing started: Thu Jul 31 18:55:06 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off vga -c vga --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "hs" as buffer
Info: Clock "clk" has Internal fmax of 89.98 MHz between source register "vs" and destination register "vga_read_dispaly~reg0" (period= 11.114 ns)
    Info: + Longest register to register delay is 0.751 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X11_Y4_N29; Fanout = 3; REG Node = 'vs'
        Info: 2: + IC(0.437 ns) + CELL(0.206 ns) = 0.643 ns; Loc. = LCCOMB_X11_Y4_N30; Fanout = 1; COMB Node = 'vga_read_dispaly~52'
        Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 0.751 ns; Loc. = LCFF_X11_Y4_N31; Fanout = 2; REG Node = 'vga_read_dispaly~reg0'
        Info: Total cell delay = 0.314 ns ( 41.81 % )
        Info: Total interconnect delay = 0.437 ns ( 58.19 % )
    Info: - Smallest clock skew is -4.542 ns
        Info: + Shortest clock path from clock "clk" to destination register is 3.103 ns
            Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_M1; Fanout = 1; CLK Node = 'clk'
            Info: 2: + IC(0.257 ns) + CELL(0.000 ns) = 1.357 ns; Loc. = CLKCTRL_G3; Fanout = 15; COMB Node = 'clk~clkctrl'
            Info: 3: + IC(1.080 ns) + CELL(0.666 ns) = 3.103 ns; Loc. = LCFF_X11_Y4_N31; Fanout = 2; REG Node = 'vga_read_dispaly~reg0'
            Info: Total cell delay = 1.766 ns ( 56.91 % )
            Info: Total interconnect delay = 1.337 ns ( 43.09 % )
        Info: - Longest clock path from clock "clk" to source register is 7.645 ns
            Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_M1; Fanout = 1; CLK Node = 'clk'
            Info: 2: + IC(0.257 ns) + CELL(0.000 ns) = 1.357 ns; Loc. = CLKCTRL_G3; Fanout = 15; COMB Node = 'clk~clkctrl'
            Info: 3: + IC(1.073 ns) + CELL(0.970 ns) = 3.400 ns; Loc. = LCFF_X12_Y5_N13; Fanout = 4; REG Node = 'hs'
            Info: 4: + IC(2.499 ns) + CELL(0.000 ns) = 5.899 ns; Loc. = CLKCTRL_G13; Fanout = 11; COMB Node = 'hs~clkctrl'
            Info: 5: + IC(1.080 ns) + CELL(0.666 ns) = 7.645 ns; Loc. = LCFF_X11_Y4_N29; Fanout = 3; REG Node = 'vs'
            Info: Total cell delay = 2.736 ns ( 35.79 % )
            Info: Total interconnect delay = 4.909 ns ( 64.21 % )
    Info: + Micro clock to output delay of source is 0.304 ns
    Info: + Micro setup delay of destination is -0.040 ns
    Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two
Info: tco from clock "clk" to destination pin "vga_vs_control" through register "vs" is 12.750 ns
    Info: + Longest clock path from clock "clk" to source register is 7.645 ns
        Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_M1; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.257 ns) + CELL(0.000 ns) = 1.357 ns; Loc. = CLKCTRL_G3; Fanout = 15; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(1.073 ns) + CELL(0.970 ns) = 3.400 ns; Loc. = LCFF_X12_Y5_N13; Fanout = 4; REG Node = 'hs'
        Info: 4: + IC(2.499 ns) + CELL(0.000 ns) = 5.899 ns; Loc. = CLKCTRL_G13; Fanout = 11; COMB Node = 'hs~clkctrl'
        Info: 5: + IC(1.080 ns) + CELL(0.666 ns) = 7.645 ns; Loc. = LCFF_X11_Y4_N29; Fanout = 3; REG Node = 'vs'
        Info: Total cell delay = 2.736 ns ( 35.79 % )
        Info: Total interconnect delay = 4.909 ns ( 64.21 % )
    Info: + Micro clock to output delay of source is 0.304 ns
    Info: + Longest register to pin delay is 4.801 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X11_Y4_N29; Fanout = 3; REG Node = 'vs'
        Info: 2: + IC(1.735 ns) + CELL(3.066 ns) = 4.801 ns; Loc. = PIN_Y1; Fanout = 0; PIN Node = 'vga_vs_control'
        Info: Total cell delay = 3.066 ns ( 63.86 % )
        Info: Total interconnect delay = 1.735 ns ( 36.14 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings
    Info: Allocated 102 megabytes of memory during processing
    Info: Processing ended: Thu Jul 31 18:55:07 2008
    Info: Elapsed time: 00:00:01