vga.saf

VGA 测试程序

# Copyright (C) 1991-2006 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, Altera MegaCore Function License 
# Agreement, or other applicable license agreement, including, 
# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
# Altera or its authorized distributors.  Please refer to the 
# applicable agreement for further details.

# Signal Activity File Name: "F:/quartus/VGA_STUDY/vga.saf"
# Created On: "07/31/2008 11:11:23"
# Created By: "Version 6.1 Build 201 11/27/2006 SJ Full Version"
# This file was created by the Quartus(R) II Simulator with glitch filtering enabled.

FORMAT_VERSION 1;

DEFINE_FLAG TOGGLE_RATE_FROM_SIMULATION 0x1;
DEFINE_FLAG STATIC_PROBABILITY_FROM_SIMULATION 0x2;
DEFINE_FLAG TOGGLE_RATE_FROM_USER 0x4;
DEFINE_FLAG STATIC_PROBABILITY_FROM_USER 0x8;
DEFINE_FLAG TOGGLE_RATE_FROM_USER_DEFAULT 0x10;
DEFINE_FLAG STATIC_PROBABILITY_FROM_USER_DEFAULT 0x20;
DEFINE_FLAG TOGGLE_RATE_FROM_VECTORLESS_ESTIMATION 0x40;
DEFINE_FLAG STATIC_PROBABILITY_FROM_VECTORLESS_ESTIMATION 0x80;
DEFINE_FLAG TOGGLE_RATE_ASSUMED_ZERO 0x100;
DEFINE_FLAG TOGGLE_RATE_CLIPPED_TO_MAX 0x200;

BEGIN_OUTPUT_SIGNAL_INFO;

# Output Signal Information Line Format Description:

# <one or more spaces><partial output signal name><spaces>[<flags mask><spaces><toggle rate><spaces><static probability>]<;>

 Add0~122 0x3 0 0;
 Add0~123 0x3 0 0;
 Add0~124 0x3 0 0;
 Add0~125 0x3 0 0.998902;
 Add0~126 0x3 0 0;
 Add0~127 0x3 0 0;
 Add0~128 0x3 0 0;
 Add0~129 0x3 0 0.998902;
 Add0~130 0x3 0 0.998396;
 Add0~131 0x3 0 0;
 Add0~132 0x3 0 0.99831;
 Add0~133 0x3 0 0.998626;
 Add0~134 0x3 0 0;
 Add0~135 0x3 0 0;
 Add0~136 0x3 0 0;
 Add0~137 0x3 0 0.999828;
 Add0~138 0x3 0 0;
 Add2~122 0x3 0 0.997778;
 Add2~123 0x3 0 0;
 Add2~124 0x3 0 0;
 Add2~125 0x3 0 0.998892;
 Add2~126 0x3 0 0;
 Add2~127 0x3 0 0;
 Add2~128 0x3 0 0;
 Add2~129 0x3 0 0.998894;
 Add2~130 0x3 0 0;
 Add2~131 0x3 0 0;
 Add2~132 0x3 0 0;
 Add2~133 0x3 0 0.998894;
 Add2~134 0x3 0 0;
 Add2~135 0x3 0 0;
 Add2~136 0x3 0 0;
 Add2~137 0x3 0 0.999484;
 Add2~138 0x3 0 0;
 clk 0x3 0 0;
 clk~clkctrl 0x3 0 0;
 Equal0~93 0x3 0 0;
 Equal0~94 0x3 0 0;
 Equal0~95 0x3 0 0;
 Equal1~57 0x3 0 0;
 Equal1~58 0x3 0 0;
 Equal2~82 0x3 0 0.998885;
 Equal2~83 0x3 0 0;
 Equal2~84 0x3 0 0;
 Equal2~85 0x3 0 0;
 GRB[1] 0x3 0 0;
 GRB[1]~31 0x3 0 0;
 hs 0x3 0 0;
 hs~77 0x3 0 0;
 hs~clkctrl 0x3 0 0;
 i[0] 0x3 0 0;
 i[0]~159 0x3 0 0.99743;
 i[1] 0x3 0 0;
 i[2] 0x3 0 0;
 i[3] 0x3 0 0;
 i[4] 0x3 0 0;
 i[5] 0x3 0 0;
 i[5]~157 0x3 0 0;
 i[6] 0x3 0 0;
 i[6]~158 0x3 0 0;
 i[7] 0x3 0 0;
 i[8] 0x3 0 0;
 i[9] 0x3 0 0;
 i~155 0x3 0 0;
 i~156 0x3 0 0;
 j[0] 0x3 0 0;
 j[0]~127 0x3 0 0.998783;
 j[1] 0x3 0 0;
 j[1]~55 0x3 0 0;
 j[1]~121 0x3 0 0;
 j[2] 0x3 0 0;
 j[2]~56 0x3 0 0;
 j[2]~122 0x3 0 0.998901;
 j[3] 0x3 0 0;
 j[3]~57 0x3 0 0;
 j[3]~123 0x3 0 0;
 j[4] 0x3 0 0;
 j[4]~58 0x3 0 0;
 j[4]~124 0x3 0 0.99889;
 j[5] 0x3 0 0;
 j[5]~59 0x3 0 0;
 j[5]~125 0x3 0 0;
 j[6] 0x3 0 0;
 j[6]~60 0x3 0 0;
 j~119 0x3 0 0;
 j~120 0x3 0 0;
 k[0] 0x3 0 0;
 k[0]~133 0x3 0 0.999607;
 k[1] 0x3 0 0;
 k[1]~132 0x3 0 0;
 k[2] 0x3 0 0;
 k[3] 0x3 0 0;
 k[4] 0x3 0 0;
 k[5] 0x3 0 0;
 k[6] 0x3 0 0;
 k[7] 0x3 0 0;
 k[8] 0x3 0 0;
 k[9] 0x3 0 0;
 LessThan0~112 0x3 0 0;
 LessThan1~94 0x3 0 0;
 reset 0x3 0 0;
 reset~clkctrl 0x3 0 0;
 vga_blue_dispaly 0x3 0 0;
 vga_green_dispaly 0x3 0 0;
 vga_hs_control 0x3 0 0.995526;
 vga_read_dispaly 0x3 0 0;
 vga_read_dispaly~52 0x3 0 0;
 vga_read_dispaly~reg0 0x3 0 0;
 vga_vs_control 0x3 0 0.995003;
 vs 0x3 0 0;
 vs~85 0x3 0 0;

END_OUTPUT_SIGNAL_INFO;

TOGGLE_PERCENTAGE 0;

PERCENTAGE_OF_TIME_SIGNALS_IN_UNKNOWN_STATE 0;