zigzag_encode.vhd

用于FPGA的Z变化算法的HDL编码

               WHEN "0000100" => scan_mem <= "0011000";    
               WHEN "0000101" => scan_mem <= "0000001";    
               WHEN "0000110" => scan_mem <= "0001001";    
               WHEN "0000111" => scan_mem <= "0000010";    
               WHEN "0001000" => scan_mem <= "0001010";    
               WHEN "0001001" => scan_mem <= "0010001";    
               WHEN "0001010" => scan_mem <= "0011001";    
               WHEN "0001011" => scan_mem <= "0100000";    
               WHEN "0001100" => scan_mem <= "0101000";    
               WHEN "0001101" => scan_mem <= "0110000";    
               WHEN "0001110" => scan_mem <= "0111000";    
               WHEN "0001111" => scan_mem <= "0000100";    
               WHEN "0010000" => scan_mem <= "0110001";    
               WHEN "0010001" => scan_mem <= "0101001";    
               WHEN "0010010" => scan_mem <= "0100001";    
               WHEN "0010011" => scan_mem <= "0011010";    
               WHEN "0010100" => scan_mem <= "0010010";    
               WHEN "0010101" => scan_mem <= "0000011";    
               WHEN "0010110" => scan_mem <= "0001011";    
               WHEN "0010111" => scan_mem <= "0000100";    
               WHEN "0011000" => scan_mem <= "0001100";    
               WHEN "0011001" => scan_mem <= "0010011";    
               WHEN "0011010" => scan_mem <= "0011011";    
               WHEN "0011011" => scan_mem <= "0100010";    
               WHEN "0011100" => scan_mem <= "0101010";    
               WHEN "0011101" => scan_mem <= "0110010";    
               WHEN "0011110" => scan_mem <= "0111010";    
               WHEN "0011111" => scan_mem <= "0100011";    
               WHEN "0100000" => scan_mem <= "0101011";    
               WHEN "0100001" => scan_mem <= "0110011";    
               WHEN "0100010" => scan_mem <= "0111011";    
               WHEN "0100011" => scan_mem <= "0010100";    
               WHEN "0100100" => scan_mem <= "0011100";    
               WHEN "0100101" => scan_mem <= "0000101";    
               WHEN "0100110" => scan_mem <= "0001101";    
               WHEN "0100111" => scan_mem <= "0000110";    
               WHEN "0101000" => scan_mem <= "0001110";    
               WHEN "0101001" => scan_mem <= "0010101";    
               WHEN "0101010" => scan_mem <= "0011101";    
               WHEN "0101011" => scan_mem <= "0100100";    
               WHEN "0101100" => scan_mem <= "0101100";    
               WHEN "0101101" => scan_mem <= "0110100";    
               WHEN "0101110" => scan_mem <= "0111100";    
               WHEN "0101111" => scan_mem <= "0100101";    
               WHEN "0110000" => scan_mem <= "0101101";    
               WHEN "0110001" => scan_mem <= "0110101";    
               WHEN "0110010" => scan_mem <= "0111101";    
               WHEN "0110011" => scan_mem <= "0010110";    
               WHEN "0110100" => scan_mem <= "0011110";    
               WHEN "0110101" => scan_mem <= "0000111";    
               WHEN "0110110" => scan_mem <= "0001111";    
               WHEN "0110111" => scan_mem <= "0010111";    
               WHEN "0111000" => scan_mem <= "0011111";    
               WHEN "0111001" => scan_mem <= "0100110";    
               WHEN "0111010" => scan_mem <= "0101110";    
               WHEN "0111011" => scan_mem <= "0110110";    
               WHEN "0111100" => scan_mem <= "0111110";    
               WHEN "0111101" => scan_mem <= "0100111";    
               WHEN "0111110" => scan_mem <= "0101111";    
               WHEN "0111111" => scan_mem <= "0110111";    
               WHEN "1000000" => scan_mem <= "0111111";    
               WHEN OTHERS => NULL;
               END CASE;
            END IF;
         END IF;
      END IF;
   END PROCESS;

   --***************************************************************************
   --qdct_in_reg1 and qdct_in_reg2 are used to store the quantised DCT values.
   --Both registers use store the same DCT values. Data from reg1 is read out in the zigzag order and data from 
   --reg2 is read out in the alternate scan order  
   
   -- read in quantised DCT value
   P_ram1: PROCESS (RST,CLK)
   BEGIN
     IF (RST = '1') THEN
         qdct_in_reg1(63 downto 0) <= (OTHERS => "000000000000");
         qdct_in_reg2(63 downto 0) <= (OTHERS => "000000000000");
     ELSIF (CLK'EVENT AND CLK = '1') THEN
         -- read out quantised DCT values in the order given in scan_mem
         IF (rdy_in = '1' AND toggle_mem = '0') THEN
            qdct_in_reg1(conv_integer(cnt64)) <= qdct_in; --"conv_integer(cnt64)",convert "cnt64" value into integer,
                                                          --from 1st process program, "cnt64" add 1 every clk, so, in
                                                          --this process, "qdct_in_reg1" add 1 every clk, to read 64
                                                          --"qdct_in" into "qdct_in_reg1" in sequence, this statement
                                                          --is somewhat like 'for(i,j,k)' statement in language C
         ELSE
            IF (rdy_in = '1' AND toggle_mem = '1') THEN
               qdct_in_reg2(conv_integer(cnt64)) <= qdct_in;    
            END IF;
         END IF;
      END IF;
   END PROCESS;

   P_ramout: PROCESS (RST,CLK)
   BEGIN
    IF (RST = '1') THEN
       zigzag_out <= (OTHERS => '0');
    ELSIF (CLK'EVENT AND CLK = '1') THEN
         IF (memread_rdy = '1' AND toggle_mem = '1') THEN
            zigzag_out <= qdct_in_reg1(conv_integer(scan_mem));    
         ELSE
            IF (memread_rdy = '1' AND toggle_mem = '0') THEN
               zigzag_out <= qdct_in_reg2(conv_integer(scan_mem));   
            ELSE
               zigzag_out <= "000000000000";    
            END IF;
         END IF;
      END IF;
   END PROCESS;

   -- END MEMORY SECTION 
   --***************************************************************************
   PROCESS (CLK, RST)
   BEGIN
      IF (RST = '1') THEN
         cnt64 <= "0000000";    
      ELSIF (CLK'EVENT AND CLK = '1') THEN
         IF (cnt64 < "1000001") THEN
            cnt64 <= cnt64 + "0000001";    
         ELSE
            cnt64 <= "0000001";    
         END IF;
      END IF;
   END PROCESS;

   --***************************************************************************
   -- memread_rdy goes active 64 clks after rdy_in is active. This is to make sure that all the 64 quantized dct 
   --input values are stored in the memory before reading it out in the zigzag order.
   PROCESS (CLK, RST)
   BEGIN
      IF (RST = '1') THEN
         memread_rdy <= '0';    
      ELSIF (CLK'EVENT AND CLK = '1') THEN
         IF (rdy_in = '1') THEN
            IF (cnt64 = "1000000") THEN
               memread_rdy <= '1';    
            ELSE
               memread_rdy <= memread_rdy;    
            END IF;
         END IF;
      END IF;
   END PROCESS;

   --***************************************************************************
   -- toggle_mem switches states every 64 clock cycles. This signal is used to choose between the 2 qdct_in_reg 
   --memories. Due to zigzag order in which data is read out, it is more efficient to have all the 64 data ready 
   --in the memory before reading it out. Since the input data is continuous, while reading out is done from one 
   --memory, the input data is redirected to the 2nd memory for the next 64 cycles..
   PROCESS (CLK, RST)
   BEGIN
      IF (RST = '1') THEN
         toggle_mem <= '0';    
      ELSIF (CLK'EVENT AND CLK = '1') THEN
         IF (rdy_in = '1') THEN
            IF (cnt64 = "1000000") THEN
               toggle_mem <= NOT toggle_mem;    
            ELSE
               toggle_mem <= toggle_mem;    
            END IF;
         END IF;
      END IF;
   END PROCESS;

   --***************************************************************************
   -- first valid zigzag output occurs when cnt64 is first hits 64 
   PROCESS (CLK, RST)
   BEGIN
      IF (RST = '1') THEN
         rdy_out1 <= '0';    
      ELSIF (CLK'EVENT AND CLK = '1') THEN
         IF (cnt64 = "1000000") THEN
            rdy_out1 <= '1';    
         ELSE
            rdy_out1 <= rdy_out1;    
         END IF;
      END IF;
   END PROCESS;

   PROCESS (CLK)
   BEGIN
      IF (CLK'EVENT AND CLK = '1') THEN
         rdy_out <= rdy_out1;    
      END IF;
   END PROCESS;
END translated;