zigzag_encode.v

用于FPGA的Z变化算法的HDL编码

Both registers use store the same DCT values. Data from reg1 is read out in the zigzag order and data from reg2 is read out in the alternate scan order  */

initial
begin
 qdct_in_reg1[0] <= 12'b0;  qdct_in_reg1[1] <= 12'b0; 
 qdct_in_reg1[2] <= 12'b0;  qdct_in_reg1[3] <= 12'b0; 
 qdct_in_reg1[4] <= 12'b0;  qdct_in_reg1[5] <= 12'b0; 
 qdct_in_reg1[6] <= 12'b0;  qdct_in_reg1[7] <= 12'b0; 
 qdct_in_reg1[8] <= 12'b0;  qdct_in_reg1[9] <= 12'b0; 
 qdct_in_reg1[10] <= 12'b0;  qdct_in_reg1[11] <= 12'b0; 
 qdct_in_reg1[12] <= 12'b0;  qdct_in_reg1[13] <= 12'b0; 
 qdct_in_reg1[14] <= 12'b0;  qdct_in_reg1[15] <= 12'b0; 
 qdct_in_reg1[16] <= 12'b0;  qdct_in_reg1[17] <= 12'b0; 
 qdct_in_reg1[18] <= 12'b0;  qdct_in_reg1[19] <= 12'b0; 
 qdct_in_reg1[20] <= 12'b0;  qdct_in_reg1[21] <= 12'b0; 
 qdct_in_reg1[22] <= 12'b0;  qdct_in_reg1[23] <= 12'b0; 
 qdct_in_reg1[24] <= 12'b0;  qdct_in_reg1[25] <= 12'b0; 
 qdct_in_reg1[26] <= 12'b0;  qdct_in_reg1[27] <= 12'b0; 
 qdct_in_reg1[28] <= 12'b0;  qdct_in_reg1[29] <= 12'b0;
 qdct_in_reg1[30] <= 12'b0;  qdct_in_reg1[31] <= 12'b0; 
 qdct_in_reg1[32] <= 12'b0;  qdct_in_reg1[33] <= 12'b0; 
 qdct_in_reg1[34] <= 12'b0;  qdct_in_reg1[35] <= 12'b0; 
 qdct_in_reg1[36] <= 12'b0;  qdct_in_reg1[37] <= 12'b0; 
 qdct_in_reg1[38] <= 12'b0;  qdct_in_reg1[39] <= 12'b0; 
 qdct_in_reg1[40] <= 12'b0;  qdct_in_reg1[41] <= 12'b0; 
 qdct_in_reg1[42] <= 12'b0;  qdct_in_reg1[43] <= 12'b0; 
 qdct_in_reg1[44] <= 12'b0;  qdct_in_reg1[45] <= 12'b0; 
 qdct_in_reg1[46] <= 12'b0;  qdct_in_reg1[47] <= 12'b0; 
 qdct_in_reg1[48] <= 12'b0;  qdct_in_reg1[49] <= 12'b0; 
 qdct_in_reg1[50] <= 12'b0;  qdct_in_reg1[51] <= 12'b0; 
 qdct_in_reg1[52] <= 12'b0;  qdct_in_reg1[53] <= 12'b0; 
 qdct_in_reg1[54] <= 12'b0;  qdct_in_reg1[55] <= 12'b0; 
 qdct_in_reg1[56] <= 12'b0;  qdct_in_reg1[57] <= 12'b0; 
 qdct_in_reg1[58] <= 12'b0;  qdct_in_reg1[59] <= 12'b0;
 qdct_in_reg1[60] <= 12'b0;  qdct_in_reg1[61] <= 12'b0; 
 qdct_in_reg1[62] <= 12'b0;  qdct_in_reg1[63] <= 12'b0;

 qdct_in_reg2[0] <= 12'b0;  qdct_in_reg2[1] <= 12'b0; 
 qdct_in_reg2[2] <= 12'b0;  qdct_in_reg2[3] <= 12'b0; 
 qdct_in_reg2[4] <= 12'b0;  qdct_in_reg2[5] <= 12'b0; 
 qdct_in_reg2[6] <= 12'b0;  qdct_in_reg2[7] <= 12'b0; 
 qdct_in_reg2[8] <= 12'b0;  qdct_in_reg2[9] <= 12'b0; 
 qdct_in_reg2[10] <= 12'b0;  qdct_in_reg2[11] <= 12'b0; 
 qdct_in_reg2[12] <= 12'b0;  qdct_in_reg2[13] <= 12'b0; 
 qdct_in_reg2[14] <= 12'b0;  qdct_in_reg2[15] <= 12'b0; 
 qdct_in_reg2[16] <= 12'b0;  qdct_in_reg2[17] <= 12'b0; 
 qdct_in_reg2[18] <= 12'b0;  qdct_in_reg2[19] <= 12'b0; 
 qdct_in_reg2[20] <= 12'b0;  qdct_in_reg2[21] <= 12'b0; 
 qdct_in_reg2[22] <= 12'b0;  qdct_in_reg2[23] <= 12'b0; 
 qdct_in_reg2[24] <= 12'b0;  qdct_in_reg2[25] <= 12'b0; 
 qdct_in_reg2[26] <= 12'b0;  qdct_in_reg2[27] <= 12'b0; 
 qdct_in_reg2[28] <= 12'b0;  qdct_in_reg2[29] <= 12'b0;
 qdct_in_reg2[30] <= 12'b0;  qdct_in_reg2[31] <= 12'b0; 
 qdct_in_reg2[32] <= 12'b0;  qdct_in_reg2[33] <= 12'b0; 
 qdct_in_reg2[34] <= 12'b0;  qdct_in_reg2[35] <= 12'b0; 
 qdct_in_reg2[36] <= 12'b0;  qdct_in_reg2[37] <= 12'b0; 
 qdct_in_reg2[38] <= 12'b0;  qdct_in_reg2[39] <= 12'b0; 
 qdct_in_reg2[40] <= 12'b0;  qdct_in_reg2[41] <= 12'b0; 
 qdct_in_reg2[42] <= 12'b0;  qdct_in_reg2[43] <= 12'b0; 
 qdct_in_reg2[44] <= 12'b0;  qdct_in_reg2[45] <= 12'b0; 
 qdct_in_reg2[46] <= 12'b0;  qdct_in_reg2[47] <= 12'b0; 
 qdct_in_reg2[48] <= 12'b0;  qdct_in_reg2[49] <= 12'b0; 
 qdct_in_reg2[50] <= 12'b0;  qdct_in_reg2[51] <= 12'b0; 
 qdct_in_reg2[52] <= 12'b0;  qdct_in_reg2[53] <= 12'b0; 
 qdct_in_reg2[54] <= 12'b0;  qdct_in_reg2[55] <= 12'b0; 
 qdct_in_reg2[56] <= 12'b0;  qdct_in_reg2[57] <= 12'b0; 
 qdct_in_reg2[58] <= 12'b0;  qdct_in_reg2[59] <= 12'b0;
 qdct_in_reg2[60] <= 12'b0;  qdct_in_reg2[61] <= 12'b0; 
 qdct_in_reg2[62] <= 12'b0;  qdct_in_reg2[63] <= 12'b0;

end
/* read in quantised DCT value: pipe1 */
always @ (posedge CLK)
   if (rdy_in == 1'b1 && toggle_mem == 1'b0)
       qdct_in_reg1[cnt64]<= qdct_in;
   else if (rdy_in == 1'b1 && toggle_mem == 1'b1)
       qdct_in_reg2[cnt64]<= qdct_in;


/* read out quantised DCT values in the order given in scan_mem :pipe2*/
always @ (posedge CLK)
  begin
     if (memread_rdy == 1'b1 && toggle_mem == 1'b1)
       zigzag_out <= qdct_in_reg1[scan_mem];
     else if (memread_rdy == 1'b1 && toggle_mem == 1'b0)
       zigzag_out <= qdct_in_reg2[scan_mem];
     else zigzag_out <= 8'b0;
  end

/* END MEMORY SECTION */

/*****************************************************************************/

always @ (posedge CLK or posedge RST)
   begin
   if (RST)
       begin
       cnt64 <= 7'b0;
       end
   else if (cnt64 < 7'b1000001)
       begin
       cnt64 <= cnt64 + 1;
       end
   else 
       begin
       cnt64 <= 7'b0000001;
       end
   end

/*****************************************************************************/

/* memread_rdy goes active 64 clks after rdy_in is active. This is to make sure that all the 64 quantized dct input values are stored in the memory before reading it out in the zigzag order.*/

always @ (posedge CLK or posedge RST)
   begin
   if (RST)
       begin
       memread_rdy <= 1'b0; 
       end
   else if (rdy_in == 1'b1)
       begin 
	   if (cnt64 == 7'b1000000)
              memread_rdy <= 1'b1; 
	   else 
              memread_rdy <= memread_rdy ; 
       end
   end

/*****************************************************************************/


/* toggle_mem switches states every 64 clock cycles. This signal is used to choose between the 2 qdct_in_reg memories. Due to zigzag order in which data is read out, it is more efficient to have all the 64 data ready in the memory before reading it out. Since the input data is continuous, while reading out is done from one memory, the input data is redirected to the 2nd memory for the next 64 cycles..*/

always @ (posedge CLK or posedge RST)
   begin
   if (RST)
       begin
       toggle_mem <= 1'b0; 
       end
   else if (rdy_in == 1'b1)
       begin 
	   if (cnt64 == 7'b1000000)
              toggle_mem <= ~toggle_mem; 
	   else 
              toggle_mem <= toggle_mem ; 
       end
   end

/*****************************************************************************/
/* first valid zigzag output occurs when cnt64 is first hits 64 */

always @ (posedge CLK or posedge RST)
   begin
   if (RST)
       begin
       rdy_out1 <= 1'b0;
       end
   else if (cnt64 == 7'b1000000)
       begin
     	 rdy_out1 <= 1'b1;
       end
   else
       begin
       rdy_out1 <= rdy_out1;
       end
   end

always @ (posedge CLK )
   begin
          rdy_out <= rdy_out1;
   end


endmodule