zigzag_encode.v

用于FPGA的Z变化算法的HDL编码

/**********************************************************************
** -----------------------------------------------------------------------
**
** zigzag.v
**
** 
**
**
**
**                  Author: Latha Pillai
**                  Senior Applications Engineer
**
**                  Video Applications
**                  Advanced Products Group
**                  Xilinx, Inc.
**
**                  Copyright (c) 2001 Xilinx, Inc.
**                  All rights reserved
**
**                  Date:   April. 10, 2002
**
**                  RESTRICTED RIGHTS LEGEND
**
**      This software has not been published by the author, and 
**      has been disclosed to others for the purpose of enhancing 
**      and promoting design productivity in Xilinx products.
**
**      Therefore use, duplication or disclosure, now and in the 
**      future should give consideration to the productivity 
**      enhancements afforded the user of this code by the author's 
**      efforts.  Thank you for using our products !
**
** Disclaimer:  THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY 
**              WHATSOEVER AND XILINX SPECIFICALLY DISCLAIMS ANY 
**              IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
**              A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.

** Module: zigzag : 

The zigzag module is used to read out the quanized dct input in a zigzag order. There are two different zigzag scanning modes in MPEG2. The scanning mode is chosen by the "scan_type" input. Scan_type = 0 chooses the default scanning mode which is also the mode used in MPEG1. MPEG2 has an alternate scanning mode which is chosen when scan_type = 1. The 2 scanning modes for an 8x8 block is as shown below

 0  1  5  6 14 15 22 28
 2  4  7 13 16 26 29 42
 3  8 12 17 25 30 41 43
 9 11 18 24 31 40 44 53
10 19 23 32 39 45 52 54
20 22 33 38 46 51 55 60
21 34 37 47 50 56 59 61
35 36 48 49 57 58 62 63



 0  4  6 20 22 36 38 52
 1  5  7 21 23 37 39 53
 2  8 19 24 34 40 50 54
 3  9 18 25 35 41 51 55
10 17 26 30 42 46 56 60
11 16 27 31 43 47 57 61
12 15 28 32 44 48 58 62
13 14 29 33 45 49 59 63

The scanning order requires that some of the later coeeficients be available in the beginning. For example, in alternate scanning mode, the 56th coeeficient is read in at the 13th clock. Also some of the initial coefficients are read out later in the cycle. For example, in alternate scanning mode, the 7th coefficient is read out only in the 52th clock cycle. Due to this nature, it is safer to have all the 64 coefficient available for 64 clock cycles. This is ensured by the memread_rdy signal. This signal waits for 64 clocks before reading out from qdct_in_reg1. By this time, all the 64 coefficients would have been stored in this memory and they are held there for 64 clocks. 

Since the input data qdct_in is continuous, we get a new value for the 1st coefficient at the 65th clock. Since the reading from qdct_in_reg1 would not be complete by the 65th clock, a second memory , qdct_in_reg2, is used to store the next set of 64 coefficients. After reading the 64 values from qdct_in_reg1, the next 64 values are read from qdct_in_reg2. This selection is done using the toggle_mem signal. This signal holds a '0' or '1' for 64 clocks and then switches. 

The values are read out from the memories depending on the value of scan_mem. Scan_mem is a register used to hold the 2 different kinds of scanning orders. Scan_type signal chooses between the 2 scanning orders.

**********************************************************************/
//scale factor --- how many bits ?
`timescale 1ns/1ps

module zigzag_encode ( CLK, RST, rdy_in, qdct_in, scan_type, zigzag_out, rdy_out);

output [11:0] zigzag_out;     /* quantised output value */
output rdy_out;
input CLK, RST;
input[11:0] qdct_in;               /* 11 bit output from DCT block */
input rdy_in;                    /* ready signal , starts quantization process                      
                                   after DCT is done for the block */ 
input scan_type;           /* used to choose b/n intra(0) & non-intra(1) 
                                   blocks */

/* signals */

reg[6:0] cnt64;
reg memread_rdy, toggle_mem;
reg[6:0] scan_mem;
reg[11:0] qdct_in_reg1[63:0], qdct_in_reg2[63:0];
reg[11:0] zigzag_out;
reg rdy_out, rdy_out1;
/*****************************************************************************/

/* scan_type register. This register is used to store the 2 different kinds of scan mode. Normal scan mode (0) is used for MPEG1 and MPEG2. Alternate scan mode (1) is used in MPEG2 for intra coded blocks */

always @ (posedge CLK)
    begin 
      if (scan_type == 1'b0)
         begin
	   case (cnt64)
         1 : begin scan_mem <= 7'd0; end   2 : begin scan_mem <= 7'd1; end 
         3 : begin scan_mem <= 7'd8; end   4 : begin scan_mem <= 7'd16; end  
         5 : begin scan_mem <= 7'd9; end   6 : begin scan_mem <= 7'd2; end  
         7 : begin scan_mem <= 7'd3; end   8 : begin scan_mem <= 7'd10; end  
         9 : begin scan_mem <= 7'd17; end  10 : begin scan_mem <= 7'd24; end  
        11 : begin scan_mem <= 7'd32; end  12 : begin scan_mem <= 7'd25; end   
        13 : begin scan_mem <= 7'd18; end  14 : begin scan_mem <= 7'd11; end  
        15 : begin scan_mem <= 7'd4; end  16 : begin scan_mem <= 7'd5; end  
        17 : begin scan_mem <= 7'd12; end  18 : begin scan_mem <= 7'd19; end  
        19 : begin scan_mem <= 7'd26; end  20 : begin scan_mem <= 7'd33; end  
        21 : begin scan_mem <= 7'd40; end  22 : begin scan_mem <= 7'd48; end  
        23 : begin scan_mem <= 7'd41; end  24 : begin scan_mem <= 7'd34; end  
        25 : begin scan_mem <= 7'd27; end  26 : begin scan_mem <= 7'd20; end  
        27 : begin scan_mem <= 7'd13; end  28 : begin scan_mem <= 7'd6; end  
        29 : begin scan_mem <= 7'd7; end  30 : begin scan_mem <= 7'd14; end  
        31 : begin scan_mem <= 7'd21; end  32 : begin scan_mem <= 7'd28; end 
        33 : begin scan_mem <= 7'd35; end  34 : begin scan_mem <= 7'd42; end  
        35 : begin scan_mem <= 7'd49; end  36 : begin scan_mem <= 7'd56; end  
        37 : begin scan_mem <= 7'd57; end  38 : begin scan_mem <= 7'd50; end  
        39 : begin scan_mem <= 7'd43; end  40 : begin scan_mem <= 7'd36; end  
        41 : begin scan_mem <= 7'd29; end  42 : begin scan_mem <= 7'd22; end   
        43 : begin scan_mem <= 7'd15; end  44 : begin scan_mem <= 7'd23; end  
        45 : begin scan_mem <= 7'd30; end  46 : begin scan_mem <= 7'd37; end  
        47 : begin scan_mem <= 7'd44; end  48 : begin scan_mem <= 7'd51; end  
        49 : begin scan_mem <= 7'd58; end  50 : begin scan_mem <= 7'd59; end  
        51 : begin scan_mem <= 7'd52; end  52 : begin scan_mem <= 7'd45; end  
        53 : begin scan_mem <= 7'd38; end  54 : begin scan_mem <= 7'd31; end  
        55 : begin scan_mem <= 7'd27; end  56 : begin scan_mem <= 7'd46; end  
        57 : begin scan_mem <= 7'd53; end  58 : begin scan_mem <= 7'd60; end  
        59 : begin scan_mem <= 7'd61; end  60 : begin scan_mem <= 7'd54; end  
        61 : begin scan_mem <= 7'd47; end  62 : begin scan_mem <= 7'd55; end   
        63 : begin scan_mem <= 7'd62; end  64 : begin scan_mem <= 7'd63; end 
        endcase
     end
     else if (scan_type == 1'b1) 
       begin
	   case (cnt64)
         1 : begin scan_mem <= 7'd0; end   2 : begin scan_mem <= 7'd8; end 
         3 : begin scan_mem <= 7'd16; end   4 : begin scan_mem <= 7'd24; end  
         5 : begin scan_mem <= 7'd1; end   6 : begin scan_mem <= 7'd9; end  
         7 : begin scan_mem <= 7'd2; end   8 : begin scan_mem <= 7'd10; end  
         9 : begin scan_mem <= 7'd17; end  10 : begin scan_mem <= 7'd25; end  
        11 : begin scan_mem <= 7'd32; end  12 : begin scan_mem <= 7'd40; end   
        13 : begin scan_mem <= 7'd48; end  14 : begin scan_mem <= 7'd56; end  
        15 : begin scan_mem <= 7'd4; end  16 : begin scan_mem <= 7'd49; end  
        17 : begin scan_mem <= 7'd41; end  18 : begin scan_mem <= 7'd33; end  
        19 : begin scan_mem <= 7'd26; end  20 : begin scan_mem <= 7'd18; end  
        21 : begin scan_mem <= 7'd3; end  22 : begin scan_mem <= 7'd11; end  
        23 : begin scan_mem <= 7'd4; end  24 : begin scan_mem <= 7'd12; end  
        25 : begin scan_mem <= 7'd19; end  26 : begin scan_mem <= 7'd27; end  
        27 : begin scan_mem <= 7'd34; end  28 : begin scan_mem <= 7'd42; end  
        29 : begin scan_mem <= 7'd50; end  30 : begin scan_mem <= 7'd58; end  
        31 : begin scan_mem <= 7'd35; end  32 : begin scan_mem <= 7'd43; end 
        33 : begin scan_mem <= 7'd51; end  34 : begin scan_mem <= 7'd59; end  
        35 : begin scan_mem <= 7'd20; end  36 : begin scan_mem <= 7'd28; end  
        37 : begin scan_mem <= 7'd5; end  38 : begin scan_mem <= 7'd13; end  
        39 : begin scan_mem <= 7'd6; end  40 : begin scan_mem <= 7'd14; end  
        41 : begin scan_mem <= 7'd21; end  42 : begin scan_mem <= 7'd29; end   
        43 : begin scan_mem <= 7'd36; end  44 : begin scan_mem <= 7'd44; end  
        45 : begin scan_mem <= 7'd52; end  46 : begin scan_mem <= 7'd60; end  
        47 : begin scan_mem <= 7'd37; end  48 : begin scan_mem <= 7'd45; end  
        49 : begin scan_mem <= 7'd53; end  50 : begin scan_mem <= 7'd61; end  
        51 : begin scan_mem <= 7'd22; end  52 : begin scan_mem <= 7'd30; end  
        53 : begin scan_mem <= 7'd7; end  54 : begin scan_mem <= 7'd15; end  
        55 : begin scan_mem <= 7'd23; end  56 : begin scan_mem <= 7'd31; end  
        57 : begin scan_mem <= 7'd38; end  58 : begin scan_mem <= 7'd46; end  
        59 : begin scan_mem <= 7'd54; end  60 : begin scan_mem <= 7'd62; end  
        61 : begin scan_mem <= 7'd39; end  62 : begin scan_mem <= 7'd47; end   
        63 : begin scan_mem <= 7'd55; end  64 : begin scan_mem <= 7'd63; end 
        endcase
	 end
end

/*****************************************************************************/

/* qdct_in_reg1 and qdct_in_reg2 are used to store the quantised DCT values.