rle_en.v

用于FPGA的变长编码算法的HDL编码

/**********************************************************************
** -----------------------------------------------------------------------
**
** rle.v
**
** Run Length Encoding
**
**
**
**                  Author: Latha Pillai
**                  Senior Applications Engineer
**
**                  Video Applications
**                  Advanced Products Group
**                  Xilinx, Inc.
**
**                  Copyright (c) 2002 Xilinx, Inc.
**                  All rights reserved
**
**                  Date:   September. 10, 2002
**
**                  RESTRICTED RIGHTS LEGEND
**
**      This software has not been published by the author, and 
**      has been disclosed to others for the purpose of enhancing 
**      and promoting design productivity in Xilinx products.
**
**      Therefore use, duplication or disclosure, now and in the 
**      future should give consideration to the productivity 
**      enhancements afforded the user of this code by the author's 
**      efforts.  Thank you for using our products !
**
** Disclaimer:  THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY 
**              WHATSOEVER AND XILINX SPECIFICALLY DISCLAIMS ANY 
**              IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
**              A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.

** Module: RLE : 

The RUN LENGTH ENCODING module is used to convert the input stream of 64 coefficients into the run of zeroes and the value. The output of the zigzag module is fed into the RLE module. The cntr_run register counts the number of zeroes in the input. When an input is a non-zero value, the value is sent out (value_out)along with the cntr_run value (run_value). Cntr64 counts up to 64 reading in each of the input value at every clock. The value read in when cntr64 is '1' is the "dc" value.

**********************************************************************/
//scale factor --- how many bits ?
`timescale 1ns/1ps

module rle_en ( CLK, RST, rdy_in, zigzag_in, dc_out, rl_out, rdy_out, eob);

output [17:0] rl_out;
output[11:0] dc_out;
output eob, rdy_out;
//output [11:0] value_out;     
//output [5:0] run_out;

input CLK, RST;
input[11:0] zigzag_in;        /* 11 bit output from DCT block */
input rdy_in;                 /* ready signal , starts quantization process                      
                                   after DCT is done for the block */ 

/* signals */

//integer N;
//reg[11:0] zigzag_in_dc;
reg[11:0] zigzag_in_ac, ac_value, mem_value;
wire[11:0] value_out;
reg[6:0] cntr64;
reg[5:0] cntr_run, cntr_run_reg;
wire[5:0] run_out;
//reg out_enable;
reg[11:0] dc_out;
//reg[17:0] ram1_mem[63:0],ram2_mem[63:0]; 
//reg[6:0] wr_cntr,rd_cntr;
wire en_ram1, en_ram2 ;
reg[17:0] rl_out;
reg eob, rdy_out;
wire  match;

/*****************************************************************************/
/* Read in coefficient. The first cofficient in the 8x8 block is the DC value. This value is sent out as zigzag_in_dc. The remaining 63 values are the AC coefficients and are sent out as zigzag_in_ac */

always @ (posedge CLK or posedge RST)
   begin
   if (RST)
        begin
        zigzag_in_ac <= 12'b0; 
		   end
   else 
       begin
       zigzag_in_ac <= zigzag_in;
       end
   end

/*****************************************************************************/
/* The AC values are checked to see if they are '0'. If zero, then the run counter
 "cntr_run" increments. This is done as long as zigzag_in_ac is zero. When the 
zigzag_in_ac is a non-zero value, the cntr_run resets to zero and the previous 
 value of cntr_run that was stored in cntr_run_reg is sent out as run_value along 
with the non-zero zigzag_in_ac value which is the ac_value. Cntr_run and cntr_run reg 
are 6 bits wide since the maximum run of zeroes in the 8x8 block is 63 
(ie. all the AC coefficients )*/

/*always @ (posedge CLK or posedge RST)
   begin
   if (RST)
       match <= 1'b0; 
   else 
       match <= (zigzag_in_ac == mem_value) ? 1'b1 : 1'b0;
   end*/

assign match = (zigzag_in_ac == mem_value) ? 1'b1 : 1'b0;

always @ (posedge CLK or posedge RST)
   begin
   if (RST)
        begin
        cntr_run_reg <= 6'b0; cntr_run <= 6'b0; 
        ac_value <= 12'b0; mem_value <= 12'b0; dc_out <= 1'b0;
        end
   else if (rdy_in == 1'b1)
        begin 
            if (cntr64 == 7'b0000001)
            begin 
			           dc_out <= zigzag_in_ac;
                  cntr_run_reg <= 6'b0;
                  ac_value <= 12'b0;
                  mem_value <= 12'b0;
                  cntr_run <= 6'b0;
               end
            else begin
               casex ({match,eob})
               //begin
                  2'b10: begin
                         cntr_run <= cntr_run + 1'b1;
                         cntr_run_reg <= 6'b0;
                         ac_value <= 12'b0;
                         dc_out <= 12'b0;
                         end
                  2'b00: begin
                         cntr_run_reg <= cntr_run;
                         ac_value <= mem_value;
                         mem_value <= zigzag_in_ac;
                         cntr_run <= 6'b0;
                         dc_out <= 12'b0;
                         end
                2'bx1: begin
                         cntr_run_reg <= cntr_run;
                         ac_value <= mem_value;
                         cntr_run <= 6'b0;
                         dc_out <= 12'b0;
                         end
                default: begin
                         cntr_run_reg <= 6'b0;
                         ac_value <= 12'b0;
                         mem_value <= 12'b0;
                         cntr_run <= 6'b0;
                         dc_out <= 12'b0;
                         end
              endcase
			  end
       end
  end
 
//assign run_out = cntr_run_reg;
//assign value_out = ac_value;

/*****************************************************************************/

  //assign rl_out = {cntr_run[5:0],ac_value[11:0]} ;

 always @ (posedge CLK or posedge RST)
   begin
   if (RST)
        begin
        rl_out <= 18'b0; 
		   end
   else 
       begin
       rl_out <= {cntr_run[5:0],ac_value[11:0]};
       end
   end

/* counter that counts upto 64. */

 always @ (posedge CLK or posedge RST)
   begin
   if (RST)
       begin
       cntr64 <= 7'b0; eob <= 1'b0;
       end
   else if (rdy_in == 1'b1)
        begin
          if (cntr64 < 7'b1000000)
              begin
              cntr64 <= cntr64 + 1;
              eob <= 1'b0;
              end
          else 
              begin
              cntr64 <= 7'b0000001;
              eob <= 1'b1;
              end
        end
  end  

/*****************************************************************************/


/*****************************************************************************/

/* rdy_out goes high after 2 clks. */

always @ (posedge CLK or posedge RST)
   begin
   if (RST)
       begin
       rdy_out <= 1'b0;
       end
   else if (rdy_in == 1'b1)
        begin
          if (cntr64 == 7'b0000010)
               rdy_out <= 1'b1;
          else 
               rdy_out <= rdy_out;
        end
  end  

/*****************************************************************************/
endmodule