rle_en.vhd

用于FPGA的变长编码算法的HDL编码

--*********************************************************************
-- *********************************************************************
-- ** -----------------------------------------------------------------------
-- **
-- ** rle.v
-- **
-- ** Run Length Encoding
-- **
-- **
-- **
-- **                  Author: Latha Pillai
-- **                  Senior Applications Engineer
-- **
-- **                  Video Applications
-- **                  Advanced Products Group
-- **                  Xilinx, Inc.
-- **
-- **                  Copyright (c) 2002 Xilinx, Inc.
-- **                  All rights reserved
-- **
-- **                  Date:   September. 10, 2002
-- **
-- **                  RESTRICTED RIGHTS LEGEND
-- **
-- **      This software has not been published by the author, and 
-- **      has been disclosed to others for the purpose of enhancing 
-- **      and promoting design productivity in Xilinx products.
-- **
-- **      Therefore use, duplication or disclosure, now and in the 
-- **      future should give consideration to the productivity 
-- **      enhancements afforded the user of this code by the author's 
-- **      efforts.  Thank you for using our products !
-- **
-- ** Disclaimer:  THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY 
-- **              WHATSOEVER AND XILINX SPECIFICALLY DISCLAIMS ANY 
-- **              IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
-- **              A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
-- ** Module: RLE : 
-- The RUN LENGTH ENCODING module is used to convert the input stream of 64 coefficients into the run of zeroes and the value. The output of the zigzag module is fed into the RLE module. The cntr_run register counts the number of zeroes in the input. When an input is a non-zero value, the value is sent out (value_out)along with the cntr_run value (run_value). Cntr64 counts up to 64 reading in each of the input value at every clock. The value read in when cntr64 is '1' is the "dc" value.
-- *********************************************************************


library IEEE; 
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;


ENTITY rle_en IS
   PORT (
      CLK                     : IN std_logic;   
      RST                     : IN std_logic;   
      rdy_in                  : IN std_logic;   
      zigzag_in               : IN std_logic_vector(11 DOWNTO 0);   --std_logic output from zig-zag block 
      dc_out                  : OUT std_logic_vector(11 DOWNTO 0);   
      rl_out                  : OUT std_logic_vector(17 DOWNTO 0);   
      rdy_out                 : OUT std_logic;   
      eob                     : OUT std_logic);   
END rle_en;

ARCHITECTURE translated OF rle_en IS

   SIGNAL zigzag_in_ac             :  std_logic_vector(11 DOWNTO 0);   
   SIGNAL ac_value                 :  std_logic_vector(11 DOWNTO 0);   
   SIGNAL mem_value                :  std_logic_vector(11 DOWNTO 0);   
   SIGNAL value_out                :  std_logic_vector(11 DOWNTO 0);   
   SIGNAL cntr64                   :  std_logic_vector(6 DOWNTO 0);   
   SIGNAL cntr_run                 :  std_logic_vector(5 DOWNTO 0);   
   SIGNAL cntr_run_reg             :  std_logic_vector(5 DOWNTO 0);   
   SIGNAL run_out                  :  std_logic_vector(5 DOWNTO 0);   
   SIGNAL en_ram1                  :  std_logic;   
   SIGNAL en_ram2                  :  std_logic;   
   SIGNAL match                    :  std_logic; 
   SIGNAL eob_reg                  :  std_logic;
   SIGNAL rdy_out_reg              :  std_logic;

--  The AC values are checked to see if they are '0'. If zero, then the run counter
--  "cntr_run" increments. This is done as long as zigzag_in_ac is zero. When the 
-- zigzag_in_ac is a non-zero value, the cntr_run resets to zero and the previous 
--  value of cntr_run that was stored in cntr_run_reg is sent out as run_value along 
-- with the non-zero zigzag_in_ac value which is the ac_value. Cntr_run and cntr_run reg 
-- are 6 bits wide since the maximum run of zeroes in the 8x8 block is 63 
-- (ie. all the AC coefficients )
   --***************************************************************************
   SIGNAL temp5               :  std_logic;   
   SIGNAL temp6               :  std_logic_vector(1 DOWNTO 0);   


BEGIN

   --***************************************************************************
   -- Read in coefficient. The first cofficient in the 8x8 block is the DC value. This value is sent out as zigzag_in_dc. The remaining 63 values are the AC coefficients and are sent out as zigzag_in_ac 
   PROCESS (CLK, RST)
   BEGIN
   rdy_out<=rdy_out_reg;
   eob<=eob_reg;
      IF (RST = '1') THEN
         zigzag_in_ac <= "000000000000";    
      ELSIF (CLK'EVENT AND CLK = '1') THEN
         zigzag_in_ac <= zigzag_in;    
      END IF;
   END PROCESS;
   temp5 <= '1' WHEN (zigzag_in_ac = mem_value) ELSE '0';
   match <= temp5 ;

   temp6 <= match & eob_reg;
   PROCESS (CLK, RST)
   BEGIN
      IF (RST = '1') THEN
         cntr_run_reg <= "000000";    
         cntr_run <= "000000";    
         ac_value <= "000000000000";    
         mem_value <= "000000000000";    
         dc_out <= "000000000000";    
      ELSIF (CLK'EVENT AND CLK = '1') THEN
         IF (rdy_in = '1') THEN
            IF (cntr64 = "0000001") THEN
               dc_out <= zigzag_in_ac;    
               cntr_run_reg <= "000000";    
               ac_value <= "000000000000";    
               mem_value <= "000000000000";    
               cntr_run <= "000000";    
            ELSE
               CASE temp6 IS
			   WHEN "10" =>
                        cntr_run <= cntr_run + "000001";    
                        cntr_run_reg <= "000000";    
                        ac_value <= "000000000000";    
                        dc_out <= "000000000000";  
               WHEN "00" =>
                        cntr_run_reg <= cntr_run;    
                        ac_value <= mem_value;    
                        mem_value <= zigzag_in_ac;    
                        cntr_run <= "000000";    
                        dc_out <= "000000000000";  
               WHEN "-1" =>
                        cntr_run_reg <= cntr_run;    
                        ac_value <= mem_value;    
                        cntr_run <= "000000";    
                        dc_out <= "000000000000";
               WHEN OTHERS =>
                        cntr_run_reg <= "000000";    
                        ac_value <= "000000000000";    
                        mem_value <= "000000000000";    
                        cntr_run <= "000000";    
                        dc_out <= "000000000000";    
               END CASE;
            END IF;
         END IF;
      END IF;
   END PROCESS;

   --assign run_out = cntr_run_reg;
   
   --assign value_out = ac_value;
   
   --***************************************************************************
   --assign rl_out = {cntr_run[5:0],ac_value[11:0]} ;
   
   PROCESS (CLK, RST)
   BEGIN
      IF (RST = '1') THEN
         rl_out <= "000000000000000000";    
      ELSIF (CLK'EVENT AND CLK = '1') THEN
         rl_out <= cntr_run(5 DOWNTO 0) & ac_value(11 DOWNTO 0);   
      END IF;
   END PROCESS;

   -- counter that counts upto 64. 
   PROCESS (CLK, RST)
   BEGIN
      IF (RST = '1') THEN
         cntr64 <= "0000000";    
         eob_reg <= '0';    
      ELSIF (CLK'EVENT AND CLK = '1') THEN
         IF (rdy_in = '1') THEN
            IF (cntr64 < "1000000") THEN
               cntr64 <= cntr64 + "0000001";    
               eob_reg <= '0';    
            ELSE
               cntr64 <= "0000001";    
               eob_reg <= '1';    
            END IF;
         END IF;
      END IF;
   END PROCESS;

   --***************************************************************************
   --***************************************************************************
   -- rdy_out goes high after 2 clks. 
   PROCESS (CLK, RST)
   BEGIN
      IF (RST = '1') THEN
         rdy_out_reg <= '0';    
      ELSIF (CLK'EVENT AND CLK = '1') THEN
         IF (rdy_in = '1') THEN
            IF (cntr64 = "0000010") THEN
               rdy_out_reg <= '1';    
            ELSE
               rdy_out_reg <= rdy_out_reg;    
            END IF;
         END IF;
      END IF;
   END PROCESS;
   --***************************************************************************

END translated;