quant.v

用于FPGA的量化算法的HDL编码

    9'd121: begin memoryQ <= 11'b00000001000;end 
    9'd122: begin memoryQ <= 11'b00000001000; end  
    9'd123: begin memoryQ <= 11'b00000001000;end 
    9'd124: begin memoryQ <= 11'b00000001000; end  
    9'd125: begin memoryQ <= 11'b00000001000;end 
    9'd126: begin memoryQ <= 11'b00000001000; end  
    9'd127: begin memoryQ <= 11'b00000001000;end 
    9'd128: begin memoryQ <= 11'b00000001000; end  
/*----------------------------------------------------------------------------*/

    9'd129: begin memoryQ <= 11'b00000000111;end 
    9'd130: begin memoryQ <= 11'b00000000111; end  
    9'd131: begin memoryQ <= 11'b00000000111;end 
    9'd132: begin memoryQ <= 11'b00000000111; end  
    9'd133: begin memoryQ <= 11'b00000000111;end 
    9'd134: begin memoryQ <= 11'b00000000111; end  
    9'd135: begin memoryQ <= 11'b00000000111;end 
    9'd136: begin memoryQ <= 11'b00000000111; end  
    9'd137: begin memoryQ <= 11'b00000000111;end 
    9'd138: begin memoryQ <= 11'b00000000111; end  
    9'd139: begin memoryQ <= 11'b00000000111;end 
    9'd140: begin memoryQ <= 11'b00000000111; end  
    9'd141: begin memoryQ <= 11'b00000000111;end 
    9'd142: begin memoryQ <= 11'b00000000111; end  
    9'd143: begin memoryQ <= 11'b00000000111;end 
    9'd144: begin memoryQ <= 11'b00000000111; end  
    9'd145: begin memoryQ <= 11'b00000000111;end 
    9'd146: begin memoryQ <= 11'b00000000111; end  
/*----------------------------------------------------------------------------*/

    9'd147: begin memoryQ <= 11'b00000000110;end 
    9'd148: begin memoryQ <= 11'b00000000110; end  
    9'd149: begin memoryQ <= 11'b00000000110;end 
    9'd150: begin memoryQ <= 11'b00000000110; end  
    9'd151: begin memoryQ <= 11'b00000000110;end 
    9'd152: begin memoryQ <= 11'b00000000110; end  
    9'd153: begin memoryQ <= 11'b00000000110;end 
    9'd154: begin memoryQ <= 11'b00000000110; end  
    9'd155: begin memoryQ <= 11'b00000000110;end 
    9'd156: begin memoryQ <= 11'b00000000110; end  
    9'd157: begin memoryQ <= 11'b00000000110;end 
    9'd158: begin memoryQ <= 11'b00000000110; end  
    9'd159: begin memoryQ <= 11'b00000000110;end 
    9'd160: begin memoryQ <= 11'b00000000110; end  
    9'd161: begin memoryQ <= 11'b00000000110;end 
    9'd162: begin memoryQ <= 11'b00000000110; end  
    9'd163: begin memoryQ <= 11'b00000000110;end 
    9'd164: begin memoryQ <= 11'b00000000110; end  
    9'd165: begin memoryQ <= 11'b00000000110;end 
    9'd166: begin memoryQ <= 11'b00000000110; end  
    9'd167: begin memoryQ <= 11'b00000000110;end 
    9'd168: begin memoryQ <= 11'b00000000110; end  
    9'd169: begin memoryQ <= 11'b00000000110;end 
    9'd170: begin memoryQ <= 11'b00000000110; end  
    9'd171: begin memoryQ <= 11'b00000000110;end 
    9'd172: begin memoryQ <= 11'b00000000101; end  
/*----------------------------------------------------------------------------*/

    9'd173: begin memoryQ <= 11'b00000000101;end 
    9'd174: begin memoryQ <= 11'b00000000101; end  
    9'd175: begin memoryQ <= 11'b00000000101;end 
    9'd176: begin memoryQ <= 11'b00000000101; end  
    9'd177: begin memoryQ <= 11'b00000000101;end 
    9'd178: begin memoryQ <= 11'b00000000101; end  
    9'd179: begin memoryQ <= 11'b00000000101;end 
    9'd180: begin memoryQ <= 11'b00000000101; end  
    9'd181: begin memoryQ <= 11'b00000000101;end 
    9'd182: begin memoryQ <= 11'b00000000101; end  
    9'd183: begin memoryQ <= 11'b00000000101;end 
    9'd184: begin memoryQ <= 11'b00000000101; end  
    9'd185: begin memoryQ <= 11'b00000000101;end 
    9'd186: begin memoryQ <= 11'b00000000101; end  
    9'd187: begin memoryQ <= 11'b00000000101;end 
    9'd188: begin memoryQ <= 11'b00000000101; end  
    9'd189: begin memoryQ <= 11'b00000000101;end 
    9'd190: begin memoryQ <= 11'b00000000101; end  
    9'd191: begin memoryQ <= 11'b00000000101;end 
    9'd192: begin memoryQ <= 11'b00000000101; end  
    9'd193: begin memoryQ <= 11'b00000000101;end 
    9'd194: begin memoryQ <= 11'b00000000101; end  
    9'd195: begin memoryQ <= 11'b00000000101;end 
    9'd196: begin memoryQ <= 11'b00000000101; end  
    9'd197: begin memoryQ <= 11'b00000000101;end 
    9'd198: begin memoryQ <= 11'b00000000101; end 
    9'd199: begin memoryQ <= 11'b00000000101;end 
    9'd200: begin memoryQ <= 11'b00000000101; end  
    9'd201: begin memoryQ <= 11'b00000000101;end 
    9'd202: begin memoryQ <= 11'b00000000101; end  
    9'd203: begin memoryQ <= 11'b00000000101;end 
    9'd204: begin memoryQ <= 11'b00000000101; end  
    9'd205: begin memoryQ <= 11'b00000000101;end 
    9'd206: begin memoryQ <= 11'b00000000101; end  
/*----------------------------------------------------------------------------*/

    9'd207: begin memoryQ <= 11'b00000000100;end 
    9'd208: begin memoryQ <= 11'b00000000100; end  
    9'd209: begin memoryQ <= 11'b00000000100;end 
    9'd210: begin memoryQ <= 11'b00000000100; end  
    9'd211: begin memoryQ <= 11'b00000000100;end 
    9'd212: begin memoryQ <= 11'b00000000100; end  
    9'd213: begin memoryQ <= 11'b00000000100;end 
    9'd214: begin memoryQ <= 11'b00000000100; end  
    9'd215: begin memoryQ <= 11'b00000000100;end 
    9'd216: begin memoryQ <= 11'b00000000100; end  
    9'd217: begin memoryQ <= 11'b00000000100;end 
    9'd218: begin memoryQ <= 11'b00000000100; end  
    9'd219: begin memoryQ <= 11'b00000000100;end 
    9'd220: begin memoryQ <= 11'b00000000100; end  
    9'd221: begin memoryQ <= 11'b00000000100;end 
    9'd222: begin memoryQ <= 11'b00000000100; end  
    9'd223: begin memoryQ <= 11'b00000000100;end 
    9'd224: begin memoryQ <= 11'b00000000100; end  
    9'd225: begin memoryQ <= 11'b00000000100;end 
    9'd226: begin memoryQ <= 11'b00000000100; end  
    9'd227: begin memoryQ <= 11'b00000000100;end 
    9'd228: begin memoryQ <= 11'b00000000100; end  
    9'd229: begin memoryQ <= 11'b00000000100;end 
    9'd230: begin memoryQ <= 11'b00000000100; end  
    9'd231: begin memoryQ <= 11'b00000000100;end 
    9'd232: begin memoryQ <= 11'b00000000100; end  
    9'd233: begin memoryQ <= 11'b00000000100;end 
    9'd234: begin memoryQ <= 11'b00000000100; end  
    9'd235: begin memoryQ <= 11'b00000000100;end 
    9'd236: begin memoryQ <= 11'b00000000100; end  
    9'd237: begin memoryQ <= 11'b00000000100;end 
    9'd238: begin memoryQ <= 11'b00000000100; end  
    9'd239: begin memoryQ <= 11'b00000000100;end 
    9'd240: begin memoryQ <= 11'b00000000100; end  
    9'd241: begin memoryQ <= 11'b00000000100;end 
    9'd242: begin memoryQ <= 11'b00000000100; end  
    9'd243: begin memoryQ <= 11'b00000000100;end 
    9'd244: begin memoryQ <= 11'b00000000100; end  
    9'd245: begin memoryQ <= 11'b00000000100;end 
    9'd246: begin memoryQ <= 11'b00000000100; end  
    9'd247: begin memoryQ <= 11'b00000000100;end 
    9'd248: begin memoryQ <= 11'b00000000100; end  
    9'd249: begin memoryQ <= 11'b00000000100;end 
    9'd250: begin memoryQ <= 11'b00000000100; end  
    9'd251: begin memoryQ <= 11'b00000000100;end 
    9'd252: begin memoryQ <= 11'b00000000100; end  
    9'd253: begin memoryQ <= 11'b00000000100;end 
    9'd254: begin memoryQ <= 11'b00000000100; end  
    9'd255: begin memoryQ <= 11'b00000000100;end 
    9'd256: begin memoryQ <= 11'b00000000100; end  
	default: begin memoryQ <= 11'b00000000000; end
    endcase
	  end
end






/*****************************************************************************/

/* [(1/Qmatrix)*(16/qscale)] => 11bits(1 + 10 decimal) * 13bits(5.8) = 24bits 
(last 18 bits being decimal plus 5 msb). Rounding off is done here and of the 
24   bits only 17 msbs are used(ie., 6 + 11 decimal). This will also enable the 
use of the multiplier in Virtex2 devices. Inputs to prod1 has 4 pipe stages each. 
Prod1 valid after 5 clk. (4 pipe stages before mult. plus 1 pipe after mult)*/

always @ (posedge CLK or posedge RST)
   begin
   if (RST)
       begin
       prod1 <= 24'b0; prod1_reg <= 24'b0;
       end
   else if (rdy_in == 1'b1)
       begin 
              prod1 <= (memoryQ* qscale_reg1); 
       end
   else 
       begin
       end
   end



/*****************************************************************************/

/* prod1 (17 bits with 6.11 decimal bits) 
   dct_out_reg (12 bits) = 17 bits. Input data is 12 bits with 1 sign and 11 data
   bits, sign extended to 17. So out of these 17 bits, only the 11 lsbs are 
   real data, the 6 msbs are sign information.
   prod2 = 17bits + 17 bits (6 + 11 decimal) = 34 bits. Of this, 11 lsbs are decimal and
   6 msbs are sign extensions. The valid output would be [27:11] = 16 bits
   after 6 clks  */

always @ (posedge CLK or posedge RST)
   begin
   if (RST)
       begin
       prod2 <= 27'b0; 
       end
   else if (rdy_in == 1'b1)
       begin 
       prod2 <= (dct_in_pipe5 * prod1[23:7]); /*27 bits, with 12 decimal */
       end
   else 
       begin
       end
   end

//assign prod2_round = prod2[28:12]; /* one decimal place is included. 17 bits */

//assign prod2_round = prod2[11] ? (prod2[27:12] + 1'b0) : prod2[27:12] ;

/*****************************************************************************/

/* compare sign magnitude of input DCT values. To match the pipeline, 
dct_out_reg should be registered once more . The section is used to calculate
k/2. k/2 = 0 for '0' dct input, k/2 =  .5 for +ve dct input and k/2 = -.5
for -ve dct input. For intra block, macroblock type = 1'b0 and k = '0'.
Prod2 has 6 pipe stages. Prod2_k occurs at the 7th clk*/

always @ (posedge CLK or posedge RST)
   begin
   if (RST)
       begin
       prod2_k <= 19'b0; 
       end
   else if (rdy_in == 1'b1 && macroblock_type_pipe6 == 1'b1)
       begin 
       if (dct_in_pipe6 == 11'b0)  
          prod2_k <= prod2[27:9]; /* 2 decimal places */
       else 
          prod2_k <= dct_in_pipe6_sign ? (prod2[27:9] - 2'b10) :
                       (prod2[27:9] + 2'b10);
       end
   else if (rdy_in == 1'b1 && macroblock_type_pipe6 == 1'b0)
       begin 
          prod2_k <= prod2[27:9]; /* 2 decimal places */
        end

   end

/*****************************************************************************/

assign prod2_round = prod2_k[1] ? (prod2_k[18:2] + 1'b1) : prod2_k[18:2] ;

/*****************************************************************************/

/* sign correction. prod2_round has 6 clk stages */

always @ (posedge CLK or posedge RST)
   begin
   if (RST)
       begin
       quant_dct_out <= 12'b0; 
       end
   else if (rdy_in == 1'b1)
       begin 
       quant_dct_out <= (dct_in_pipe7_sign) ? (-prod2_round[11:0]) : (prod2_round[11:0]); 
       end
   end

/*****************************************************************************/

/* Ist valid ouput occurs after 6 clks*/

always @ (posedge CLK or posedge RST)
   begin
   if (RST)
       begin
       quant_rdy_out <= 1'b0;
       end
   else if (cnt6 == 4'b0111) /* changed from 111 on sept26,02 */
       begin 
       quant_rdy_out <= 1'b1;
       end
   end


endmodule

/*****************************************************************************/