quant.v

用于FPGA的量化算法的HDL编码

       macroblock_type_pipe6 <= 1'b0;macroblock_type_pipe7 <= 1'b0;
       macroblock_type_pipe8 <= 1'b0;
       end
     else 
       begin
       macroblock_type_pipe2 <= macroblock_type_reg1;
       macroblock_type_pipe3 <= macroblock_type_pipe2;
       macroblock_type_pipe4 <= macroblock_type_pipe3;
       macroblock_type_pipe5 <= macroblock_type_pipe4;
       macroblock_type_pipe6 <= macroblock_type_pipe5;
       macroblock_type_pipe7 <= macroblock_type_pipe6;
       macroblock_type_pipe8 <= macroblock_type_pipe7;
       end
   end

/*****************************************************************************/

/* read in dct values: pipe1 */
always @ (posedge CLK or posedge RST)
   begin
   if (RST)
       begin
       dct_in_pipe1 <= 12'b0; 
       end
   else if (rdy_in == 1'b1)
       begin
       dct_in_pipe1 <= dct_in;
       end
   end
/* register dct_out_reg . This is done to match the pipeline stage with that of 
   prod1 which has 4 pipe stages at the output of first multiplier . the 11th  
   bit is registered once more to match the pipe stage in the calculation of  
   prod2_sign */

always @ (posedge CLK or posedge RST)
   begin
   if (RST)
       begin
       dct_in_pipe2 <= 11'b0; dct_in_pipe2_sign <= 1'b0;
       dct_in_pipe3 <= 11'b0; dct_in_pipe3_sign <= 1'b0;
       dct_in_pipe4 <= 11'b0; dct_in_pipe4_sign <= 1'b0;
       dct_in_pipe5 <= 11'b0; dct_in_pipe5_sign <= 1'b0;
       dct_in_pipe6 <= 11'b0; dct_in_pipe6_sign <= 1'b0;
       dct_in_pipe7 <= 11'b0; dct_in_pipe7_sign <= 1'b0;
       dct_in_pipe8_sign <= 1'b0; dct_in_pipe9_sign <= 1'b0;
       end
   else 
       begin
       dct_in_pipe2 <= dct_in_pipe1[11] ? (-dct_in_pipe1[10:0]) : dct_in_pipe1[10:0];
       dct_in_pipe2_sign <= dct_in_pipe1[11];
       dct_in_pipe3 <= dct_in_pipe2;
       dct_in_pipe3_sign <= dct_in_pipe2_sign;
       dct_in_pipe4 <= dct_in_pipe3;
       dct_in_pipe4_sign <= dct_in_pipe3_sign;
       dct_in_pipe5 <= dct_in_pipe4;
       dct_in_pipe5_sign <= dct_in_pipe4_sign;
       dct_in_pipe6 <= dct_in_pipe5;
       dct_in_pipe6_sign <= dct_in_pipe5_sign;
       dct_in_pipe7 <= dct_in_pipe6;
       dct_in_pipe7_sign <= dct_in_pipe6_sign;
       dct_in_pipe8_sign <= dct_in_pipe7_sign;
       dct_in_pipe9_sign <= dct_in_pipe8_sign;
       end
   end
/*****************************************************************************/

/* store 32/(2*quant_scale_code) in q_scale_mem1 and q_scale_mem2. Q_scale_type is 
used to choose between the 2 memories. q_scale_mem output active after 3 clks
2clk pipe stages for the qscale_mem_sel signal, 1 more clk for the q_scale_mem
output signal */

assign qscale_mem_sel = {cnt_start,quant_scale_type_reg2,quant_scale_code_reg2};

always @ (posedge CLK)
  // begin
  // if (RST)
  //     begin
  //     q_scale_mem <= 13'b0; 
  //     end
   //else if (cnt_start == 1'b1 && quant_scale_type_reg1 == 1'b0) 
       begin
	   case (qscale_mem_sel)
        7'b1000001 : begin q_scale_mem <= 13'b100000000000; end /* 2; 8      */    
        7'b1000010 : begin q_scale_mem <= 13'b010000000000; end /* 4; 4      */
        7'b1000011 : begin q_scale_mem <= 13'b001010101010; end /* 6; 2.667  */   
        7'b1000100 : begin q_scale_mem <= 13'b001000000000; end /* 8; 2      */
        7'b1000101 : begin q_scale_mem <= 13'b000110011001; end /* 10; 1.6   */ 
        7'b1000110 : begin q_scale_mem <= 13'b000101010111; end /* 12; 1.334 */
        7'b1000111 : begin q_scale_mem <= 13'b000100100011; end /* 14; 1.142 */
        7'b1001000 : begin q_scale_mem <= 13'b000100000000; end /* 16; 1     */
        7'b1001001 : begin q_scale_mem <= 13'b000011100011; end /* 18; 0.889 */ 
        7'b1001010 : begin q_scale_mem <= 13'b000011001100; end /* 20; 0.8   */
        7'b1001011 : begin q_scale_mem <= 13'b000010111010; end /* 22; 0.727 */
        7'b1001100 : begin q_scale_mem <= 13'b000010101010; end /* 24; 0.667 */
        7'b1001101 : begin q_scale_mem <= 13'b000010011101; end /* 26; 0.615 */
        7'b1001110 : begin q_scale_mem <= 13'b000010010010; end /* 28; 0.571 */
        7'b1001111 : begin q_scale_mem <= 13'b000010001000; end /* 30; 0.534 */
        7'b1010000 : begin q_scale_mem <= 13'b000010000000; end /* 32; 0.5   */
        7'b1010001 : begin q_scale_mem <= 13'b000001111000; end /* 34; 0.470 */
        7'b1010010 : begin q_scale_mem <= 13'b000001110001; end /* 36; 0.445 */
        7'b1010011 : begin q_scale_mem <= 13'b000001101011; end /* 38; 0.421 */
        7'b1010100 : begin q_scale_mem <= 13'b000001100110; end /* 40; 0.4   */
        7'b1010101 : begin q_scale_mem <= 13'b000001100001; end /* 42; 0.380 */
        7'b1010110 : begin q_scale_mem <= 13'b000001011101; end /* 44; 0.364 */
        7'b1010111 : begin q_scale_mem <= 13'b000001011001; end /* 46; 0.348 */
        7'b1011000 : begin q_scale_mem <= 13'b000001010101; end /* 48; 0.334 */
        7'b1011001 : begin q_scale_mem <= 13'b000001010001; end /* 50; 0.32  */
        7'b1011010 : begin q_scale_mem <= 13'b000001001110; end /* 52; 0.308 */
        7'b1011011 : begin q_scale_mem <= 13'b000001001011; end /* 54; 0.296 */
        7'b1011100 : begin q_scale_mem <= 13'b000001001001; end /* 56; 0.286 */
        7'b1011101 : begin q_scale_mem <= 13'b000001000110; end /* 58; 0.276 */
        7'b1011110 : begin q_scale_mem <= 13'b000001000100; end /* 60; 0.267 */
        7'b1011111 : begin q_scale_mem <= 13'b000001000010; end /* 62; 0.258 */

        7'b1100001 : begin q_scale_mem <= 13'b1000000000000; end /* 1; 16 */ 
        7'b1100010 : begin q_scale_mem <= 13'b100000000000; end /* 2; 8 */ 
        7'b1100011 : begin q_scale_mem <= 13'b000001010101; end /* 3; 5.334 */ 
        7'b1100100 : begin q_scale_mem <= 13'b010000000000; end /* 4; 4 */ 
        7'b1100101 : begin q_scale_mem <= 13'b000000110011; end /* 5; 3.2 */ 
        7'b1100110 : begin q_scale_mem <= 13'b001010101010; end /* 6; 2.667 */ 
        7'b1100111 : begin q_scale_mem <= 13'b000001001001; end /* 7; 2.286 */ 
        7'b1101000 : begin q_scale_mem <= 13'b001000000000; end /* 8; 2 */ 
        7'b1101001 : begin q_scale_mem <= 13'b000110011001; end /* 10; 1.6 */ 
        7'b1101010 : begin q_scale_mem <= 13'b000101010111; end /* 12; 1.334 */ 
        7'b1101011 : begin q_scale_mem <= 13'b000100100011; end /* 14; 1.143 */ 
        7'b1101100 : begin q_scale_mem <= 13'b000100000000; end /* 16; 1 */ 
        7'b1101101 : begin q_scale_mem <= 13'b000011100011; end /* 18; 0.889 */ 
        7'b1101110 : begin q_scale_mem <= 13'b000011001100; end /* 20; 0.8 */ 
        7'b1101111 : begin q_scale_mem <= 13'b000010111010; end /* 22; 0.727 */ 
        7'b1110000 : begin q_scale_mem <= 13'b000010101010; end /* 24; 0.667 */ 
        7'b1110001 : begin q_scale_mem <= 13'b000010010010; end /* 28; 0.571 */ 
        7'b1110010 : begin q_scale_mem <= 13'b000010000000; end /* 32; 0.5 */ 
        7'b1110011 : begin q_scale_mem <= 13'b000001110001; end /* 36; 0.445 */ 
        7'b1110100 : begin q_scale_mem <= 13'b000001100110; end /* 40; 0.4 */ 
        7'b1110101 : begin q_scale_mem <= 13'b000001011101; end /* 44; 0.364 */ 
        7'b1110110 : begin q_scale_mem <= 13'b000001010101; end /* 48; 0.334 */ 
        7'b1110111 : begin q_scale_mem <= 13'b000001001110; end /* 52; 0.308 */ 
        7'b1111000 : begin q_scale_mem <= 13'b000001001001; end /* 56; 0.286 */ 
        7'b1111001 : begin q_scale_mem <= 13'b000001000000; end /* 64; 0.25 */ 
        7'b1111010 : begin q_scale_mem <= 13'b000000111000; end /* 72; 0.222 */ 
        7'b1111011 : begin q_scale_mem <= 13'b000000110011; end /* 80; 0.2 */ 
        7'b1111100 : begin q_scale_mem <= 13'b000000101110; end /* 88; 0.182 */ 
        7'b1111101 : begin q_scale_mem <= 13'b000000101010; end /* 96; 0.167 */ 
        7'b1111110 : begin q_scale_mem <= 13'b000000100111; end /* 104; 0.154 */ 
        7'b1111111 : begin q_scale_mem <= 13'b000000100100; end /* 112; 0.143 */ 

          default: begin q_scale_mem <= 13'b000000000000; end
        endcase
	 end
//end

/*qscale_reg1 active after 4 clks */

always @ (posedge CLK or posedge RST)
   begin
   if (RST)
       begin
       qscale_reg1 <= 13'b0; 
       end
   else if (rdy_in == 1'b1)
       begin
       qscale_reg1 <= q_scale_mem;
       end
   end


/* qscale_reg2 active after 5 clks */
always @ (posedge CLK or posedge RST)
   begin
     if (RST)
       begin
       qscale_reg2 <= 13'b0; 
       end
     else 
       begin
       qscale_reg2 <= qscale_reg1; 
       end
   end



/*****************************************************************************/
/*****************************************************************************/
/*****************************************************************************/
/* Two 64x8 memories to store the default intra and non-intra Qmatrix. 1clk for
the def_qmem_sel signal, 2nd clk for the def_q_mem signal. */

assign def_qmem_sel = {cnt_start,macroblock_type_reg1,cnt64b};

always @ (posedge CLK)
   begin
	   casex (def_qmem_sel) //(cnt64b)
        9'b101000000: begin def_q_mem <= /* 8'b 00001000; end */ 8'd8;  end     
        9'b100000001: begin def_q_mem <= /* 8'b 00000000; end */ 8'd16; end 
        9'b100000010: begin def_q_mem <= /* 8'b 00000000; end */ 8'd19; end     
        9'b100000011: begin def_q_mem <= /* 8'b 00000000; end */ 8'd22; end 
        9'b100000100: begin def_q_mem <= /* 8'b 00000000; end */ 8'd26; end     
        9'b100000101: begin def_q_mem <= /* 8'b 00000000; end */ 8'd27; end 
        9'b100000110: begin def_q_mem <= /* 8'b 00000000; end */ 8'd29; end    
        9'b100000111: begin def_q_mem <= /* 8'b 00000000; end */ 8'd34; end 
        9'b100001000: begin def_q_mem <= /* 8'b 00000000; end */ 8'd16; end    
        9'b100001001: begin def_q_mem <= /* 8'b 00000000; end */ 8'd16; end 
        9'b100001010: begin def_q_mem <= /* 8'b 00000000; end */ 8'd22; end    
        9'b100001011: begin def_q_mem <= /* 8'b 00000000; end */ 8'd24; end 
        9'b100001100: begin def_q_mem <= /* 8'b 00000000; end */ 8'd27; end   
        9'b100001101: begin def_q_mem <= /* 8'b 00000000; end */ 8'd29; end 
        9'b100001110: begin def_q_mem <= /* 8'b 00000000; end */ 8'd34; end    
        9'b100001111: begin def_q_mem <= /* 8'b 00000000; end */ 8'd37; end 
        9'b100010000: begin def_q_mem <= /* 8'b 00000000; end */ 8'd19;  end     
        9'b100010001: begin def_q_mem <= /* 8'b 00000000; end */ 8'd22; end 
        9'b100010010: begin def_q_mem <= /* 8'b 00000000; end */ 8'd26; end     
        9'b100010011: begin def_q_mem <= /* 8'b 00000000; end */ 8'd27; end 
        9'b100010100: begin def_q_mem <= /* 8'b 00000000; end */ 8'd29; end     
        9'b100010101: begin def_q_mem <= /* 8'b 00000000; end */ 8'd34; end 
        9'b100010110: begin def_q_mem <= /* 8'b 00000000; end */ 8'd34; end    
        9'b100010111: begin def_q_mem <= /* 8'b 00000000; end */ 8'd38; end 
        9'b100011000: begin def_q_mem <= /* 8'b 00000000; end */ 8'd22; end    
        9'b100011001: begin def_q_mem <= /* 8'b 00000000; end */ 8'd22; end 
        9'b100011010: begin def_q_mem <= /* 8'b 00000000; end */ 8'd26; end    
        9'b100011011: begin def_q_mem <= /* 8'b 00000000; end */ 8'd27; end 
        9'b100011100: begin def_q_mem <= /* 8'b 00000000; end */ 8'd29; end   
        9'b100011101: begin def_q_mem <= /* 8'b 00000000; end */ 8'd34; end 
        9'b100011110: begin def_q_mem <= /* 8'b 00000000; end */ 8'd37; end    
        9'b100011111: begin def_q_mem <= /* 8'b 00000000; end */ 8'd40; end 
        9'b100100000: begin def_q_mem <= /* 8'b 00000000; end */ 8'd22; end   
        9'b100100001: begin def_q_mem <= /* 8'b 00000000; end */ 8'd26; end 
        9'b100100010: begin def_q_mem <= /* 8'b 00000000; end */ 8'd27; end    
        9'b100100011: begin def_q_mem <= /* 8'b 00000000; end */ 8'd29; end 
        9'b100100100: begin def_q_mem <= /* 8'b 00000000; end */ 8'd32;  end     
        9'b100100101: begin def_q_mem <= /* 8'b 00000000; end */ 8'd35; end 
        9'b100100110: begin def_q_mem <= /* 8'b 00000000; end */ 8'd40; end     
        9'b100100111: begin def_q_mem <= /* 8'b 00000000; end */ 8'd48; end 
        9'b100101000: begin def_q_mem <= /* 8'b 00000000; end */ 8'd26; end     
        9'b100101001: begin def_q_mem <= /* 8'b 00000000; end */ 8'd27; end 
        9'b100101010: begin def_q_mem <= /* 8'b 00000000; end */ 8'd29; end    
        9'b100101011: begin def_q_mem <= /* 8'b 00000000; end */ 8'd32; end 
        9'b100101100: begin def_q_mem <= /* 8'b 00000000; end */ 8'd35; end    
        9'b100101101: begin def_q_mem <= /* 8'b 00000000; end */ 8'd40; end 
        9'b100101110: begin def_q_mem <= /* 8'b 00000000; end */ 8'd48; end    
        9'b100101111: begin def_q_mem <= /* 8'b 00000000; end */ 8'd58; end 
        9'b100110000: begin def_q_mem <= /* 8'b 00000000; end */ 8'd26; end   
        9'b100110001: begin def_q_mem <= /* 8'b 00000000; end */ 8'd27; end 
        9'b100110010: begin def_q_mem <= /* 8'b 00000000; end */ 8'd29; end    
        9'b100110011: begin def_q_mem <= /* 8'b 00000000; end */ 8'd34; end 
        9'b100110100: begin def_q_mem <= /* 8'b 00000000; end */ 8'd38; end   
        9'b100110101: begin def_q_mem <= /* 8'b 00000000; end */ 8'd46; end 
        9'b100110110: begin def_q_mem <= /* 8'b 00000000; end */ 8'd56; end    
        9'b100110111: begin def_q_mem <= /* 8'b 00000000; end */ 8'd69; end 
        9'b100111000: begin def_q_mem <= /* 8'b 00000000; end */ 8'd27; end     
        9'b100111001: begin def_q_mem <= /* 8'b 00000000; end */ 8'd29; end 
        9'b100111010: begin def_q_mem <= /* 8'b 00000000; end */ 8'd35; end     
        9'b100111011: begin def_q_mem <= /* 8'b 00000000; end */ 8'd38; end 
        9'b100111100: begin def_q_mem <= /* 8'b 00000000; end */ 8'd46; end     
        9'b100111101: begin def_q_mem <= /* 8'b 00000000; end */ 8'd56; end 
        9'b100111110: begin def_q_mem <= /* 8'b 00000000; end */ 8'd69; end    
        9'b100111111: begin def_q_mem <= /* 8'b 00000000; end */ 8'd83; end 
		   9'b11xxxxxxx: begin def_q_mem <= /* 8'b 00000000; end */ 8'd16; end
  	       default: begin def_q_mem <= 8'd0; end
		   endcase
end


/*****************************************************************************/
/* q_value_select uses q_value_new_out,def_q_mem and load_intra and load_non_intra
signals. q_value_new_out has 2 clk stages,def_q_mem has 2 clk stages, load_intra_reg2
and load_non_intra_reg2 has 2 clk stages*/
/* DELETE */
/* register def_q_mem . This is done to match the pipeline stage with that of 
   qscale code and the user defined Q matrix which has 3 pipe stages before the 
   first multiplier : pipe2*/

always @ (posedge CLK or posedge RST)
   begin
   if (RST)
       begin
       def_q_mem_reg1 <= 7'b0; def_q_mem_reg2 <= 7'b0;
       def_q_mem_reg3 <= 7'b0;
       end
   else 
       begin
       def_q_mem_reg1 <= def_q_mem; 
       def_q_mem_reg2 <= def_q_mem_reg1;