uart.flow.rpt

在ＶＨＤＬ上编写了UART通信协议

Flow report for UART
Sat Jun 02 11:06:55 2007
Version 5.1 Build 176 10/26/2005 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Flow Summary
  3. Flow Settings
  4. Flow Elapsed Time
  5. Flow Log



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+--------------------------------------------------------------------+
; Flow Summary                                                       ;
+--------------------------+-----------------------------------------+
; Flow Status              ; Successful - Sat Jun 02 11:06:55 2007   ;
; Quartus II Version       ; 5.1 Build 176 10/26/2005 SJ Web Edition ;
; Revision Name            ; UART                                    ;
; Top-level Entity Name    ; UART                                    ;
; Family                   ; Stratix                                 ;
; Met timing requirements  ; Yes                                     ;
; Total logic elements     ; 92 / 10,570 ( < 1 % )                   ;
; Total pins               ; 20 / 336 ( 6 % )                        ;
; Total virtual pins       ; 0                                       ;
; Total memory bits        ; 0 / 920,448 ( 0 % )                     ;
; DSP block 9-bit elements ; 0 / 48 ( 0 % )                          ;
; Total PLLs               ; 0 / 6 ( 0 % )                           ;
; Total DLLs               ; 0 / 2 ( 0 % )                           ;
; Device                   ; EP1S10F484C5                            ;
; Timing Models            ; Final                                   ;
+--------------------------+-----------------------------------------+


+-----------------------------------------+
; Flow Settings                           ;
+-------------------+---------------------+
; Option            ; Setting             ;
+-------------------+---------------------+
; Start date & time ; 06/02/2007 09:03:08 ;
; Main task         ; Compilation         ;
; Revision Name     ; UART                ;
+-------------------+---------------------+


+-------------------------------------+
; Flow Elapsed Time                   ;
+----------------------+--------------+
; Module Name          ; Elapsed Time ;
+----------------------+--------------+
; Analysis & Synthesis ; 00:00:06     ;
; Partition Merge      ; 00:00:01     ;
; Fitter               ; 00:00:15     ;
; Assembler            ; 00:00:05     ;
; Timing Analyzer      ; 00:00:01     ;
; Analysis & Synthesis ; 00:00:05     ;
; Partition Merge      ; 00:00:02     ;
; Fitter               ; 00:00:14     ;
; Assembler            ; 00:00:05     ;
; Timing Analyzer      ; 00:00:02     ;
; Analysis & Synthesis ; 00:00:06     ;
; Partition Merge      ; 00:00:01     ;
; Fitter               ; 00:00:15     ;
; Assembler            ; 00:00:06     ;
; Timing Analyzer      ; 00:00:01     ;
; Analysis & Synthesis ; 00:00:06     ;
; Partition Merge      ; 00:00:01     ;
; Fitter               ; 00:00:14     ;
; Assembler            ; 00:00:06     ;
; Timing Analyzer      ; 00:00:02     ;
; Analysis & Synthesis ; 00:00:06     ;
; Partition Merge      ; 00:00:02     ;
; Fitter               ; 00:00:14     ;
; Assembler            ; 00:00:05     ;
; Timing Analyzer      ; 00:00:02     ;
; Total                ; 00:02:23     ;
+----------------------+--------------+


------------
; Flow Log ;
------------
quartus_map --read_settings_files=on --write_settings_files=off UART -c UART
quartus_cdb UART -c UART --merge=on
quartus_fit --read_settings_files=off --write_settings_files=off UART -c UART
quartus_asm --read_settings_files=off --write_settings_files=off UART -c UART
quartus_tan --read_settings_files=off --write_settings_files=off UART -c UART --timing_analysis_only
quartus_map --read_settings_files=on --write_settings_files=off UART -c UART
quartus_cdb UART -c UART --merge=on
quartus_fit --read_settings_files=off --write_settings_files=off UART -c UART
quartus_asm --read_settings_files=off --write_settings_files=off UART -c UART
quartus_tan --read_settings_files=off --write_settings_files=off UART -c UART --timing_analysis_only
quartus_map --read_settings_files=on --write_settings_files=off UART -c UART
quartus_cdb UART -c UART --merge=on
quartus_fit --read_settings_files=off --write_settings_files=off UART -c UART
quartus_asm --read_settings_files=off --write_settings_files=off UART -c UART
quartus_tan --read_settings_files=off --write_settings_files=off UART -c UART --timing_analysis_only
quartus_map --read_settings_files=on --write_settings_files=off UART -c UART
quartus_cdb UART -c UART --merge=on
quartus_fit --read_settings_files=off --write_settings_files=off UART -c UART
quartus_asm --read_settings_files=off --write_settings_files=off UART -c UART
quartus_tan --read_settings_files=off --write_settings_files=off UART -c UART --timing_analysis_only
quartus_map --read_settings_files=on --write_settings_files=off UART -c UART
quartus_cdb UART -c UART --merge=on
quartus_fit --read_settings_files=off --write_settings_files=off UART -c UART
quartus_asm --read_settings_files=off --write_settings_files=off UART -c UART
quartus_tan --read_settings_files=off --write_settings_files=off UART -c UART --timing_analysis_only