uart.fit.rpt

在ＶＨＤＬ上编写了UART通信协议

Fitter report for UART
Sat Jun 02 11:06:46 2007
Version 5.1 Build 176 10/26/2005 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Fitter Summary
  3. Fitter Settings
  4. Fitter Device Options
  5. Fitter Netlist Optimizations
  6. Fitter Equations
  7. Pin-Out File
  8. Fitter Resource Usage Summary
  9. Input Pins
 10. Output Pins
 11. Bidir Pins
 12. I/O Bank Usage
 13. All Package Pins
 14. Output Pin Default Load For Reported TCO
 15. Fitter Resource Utilization by Entity
 16. Delay Chain Summary
 17. Pad To Core Delay Chain Fanout
 18. Control Signals
 19. Global & Other Fast Signals
 20. Non-Global High Fan-Out Signals
 21. Interconnect Usage Summary
 22. LAB Logic Elements
 23. LAB-wide Signals
 24. LAB Signals Sourced
 25. LAB Signals Sourced Out
 26. LAB Distinct Inputs
 27. Fitter Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+--------------------------------------------------------------------+
; Fitter Summary                                                     ;
+--------------------------+-----------------------------------------+
; Fitter Status            ; Successful - Sat Jun 02 11:06:46 2007   ;
; Quartus II Version       ; 5.1 Build 176 10/26/2005 SJ Web Edition ;
; Revision Name            ; UART                                    ;
; Top-level Entity Name    ; UART                                    ;
; Family                   ; Stratix                                 ;
; Device                   ; EP1S10F484C5                            ;
; Timing Models            ; Final                                   ;
; Total logic elements     ; 92 / 10,570 ( < 1 % )                   ;
; Total pins               ; 20 / 336 ( 6 % )                        ;
; Total virtual pins       ; 0                                       ;
; Total memory bits        ; 0 / 920,448 ( 0 % )                     ;
; DSP block 9-bit elements ; 0 / 48 ( 0 % )                          ;
; Total PLLs               ; 0 / 6 ( 0 % )                           ;
; Total DLLs               ; 0 / 2 ( 0 % )                           ;
+--------------------------+-----------------------------------------+


+------------------------------------------------------------------------------------------------------------------------+
; Fitter Settings                                                                                                        ;
+------------------------------------------------------+--------------------------------+--------------------------------+
; Option                                               ; Setting                        ; Default Value                  ;
+------------------------------------------------------+--------------------------------+--------------------------------+
; Device                                               ; AUTO                           ;                                ;
; SignalProbe signals routed during normal compilation ; Off                            ; Off                            ;
; Use smart compilation                                ; Off                            ; Off                            ;
; Router Timing Optimization Level                     ; Normal                         ; Normal                         ;
; Placement Effort Multiplier                          ; 1.0                            ; 1.0                            ;
; Router Effort Multiplier                             ; 1.0                            ; 1.0                            ;
; Optimize Hold Timing                                 ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;
; Optimize Fast-Corner Timing                          ; Off                            ; Off                            ;
; Optimize Timing                                      ; Normal compilation             ; Normal compilation             ;
; Optimize IOC Register Placement for Timing           ; On                             ; On                             ;
; Limit to One Fitting Attempt                         ; Off                            ; Off                            ;
; Final Placement Optimizations                        ; Automatically                  ; Automatically                  ;
; Fitter Aggressive Routability Optimizations          ; Automatically                  ; Automatically                  ;
; Fitter Initial Placement Seed                        ; 1                              ; 1                              ;
; Slow Slew Rate                                       ; Off                            ; Off                            ;
; PCI I/O                                              ; Off                            ; Off                            ;
; Weak Pull-Up Resistor                                ; Off                            ; Off                            ;
; Enable Bus-Hold Circuitry                            ; Off                            ; Off                            ;