uart.map.summary

在ＶＨＤＬ上编写了UART通信协议

Analysis & Synthesis Status : Successful - Sat Jun 02 11:06:28 2007
Quartus II Version : 5.1 Build 176 10/26/2005 SJ Web Edition
Revision Name : UART
Top-level Entity Name : UART
Family : Stratix
Total logic elements : N/A until Partition Merge
Total pins : N/A until Partition Merge
Total virtual pins : N/A until Partition Merge
Total memory bits : N/A until Partition Merge
DSP block 9-bit elements : N/A until Partition Merge
Total PLLs : N/A until Partition Merge
Total DLLs : N/A until Partition Merge