uart.map.rpt

在ＶＨＤＬ上编写了UART通信协议

; Ignore translate_off and translate_on Synthesis Directives         ; Off                ; Off                ;
; Show Parameter Settings Tables in Synthesis Report                 ; On                 ; On                 ;
; Ignore Maximum Fan-Out Assignments                                 ; Off                ; Off                ;
; Retiming Meta-Stability Register Sequence Length                   ; 2                  ; 2                  ;
; PowerPlay Power Optimization                                       ; Normal compilation ; Normal compilation ;
; HDL message level                                                  ; Level2             ; Level2             ;
+--------------------------------------------------------------------+--------------------+--------------------+


+---------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                            ;
+----------------------------------+-----------------+-----------+----------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path     ;
+----------------------------------+-----------------+-----------+----------------------------------+
; UART.vhd                         ; yes             ; Other     ; C:/mywork/04058095/UART/UART.vhd ;
+----------------------------------+-----------------+-----------+----------------------------------+


+---------------------------+
; Partition Dependent Files ;
+---------------------------+
; Dependent Files:          ;
+---------------------------+
; UART.vhd                  ;
+---------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                           ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 3:1                ; 9 bits    ; 18 LEs        ; 9 LEs                ; 9 LEs                  ; Yes        ; |UART|t_shift[9]           ;
; 4:1                ; 4 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; Yes        ; |UART|cnt[3]               ;
; 10:1               ; 2 bits    ; 12 LEs        ; 4 LEs                ; 8 LEs                  ; Yes        ; |UART|sst[1]               ;
; 4:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; Yes        ; |UART|over[1]              ;
; 11:1               ; 2 bits    ; 14 LEs        ; 6 LEs                ; 8 LEs                  ; Yes        ; |UART|ssr[2]               ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+


+---------------------------------------------------+
; User-Specified and Inferred Latches               ;
+-----------------------------------------------+---+
; Latch Name                                    ;   ;
+-----------------------------------------------+---+
; tbuf[0]                                       ;   ;
; tbuf[1]                                       ;   ;
; tbuf[2]                                       ;   ;
; tbuf[3]                                       ;   ;
; tbuf[4]                                       ;   ;
; tbuf[5]                                       ;   ;
; tbuf[6]                                       ;   ;
; tbuf[7]                                       ;   ;
; Number of user-specified and inferred latches ; 8 ;
+-----------------------------------------------+---+
Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Partition for Top-Level Resource Utilization by Entity                                                                                                                                                                                                  ;
+----------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; |UART                      ; 101 (101)   ; 54           ; 0           ; 0            ; 0       ; 0         ; 0         ; 8    ; 0            ; 47 (47)      ; 18 (18)           ; 36 (36)          ; 4 (4)           ; 0 (0)      ; |UART               ;
+----------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in C:/mywork/04058095/UART/UART.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.1 Build 176 10/26/2005 SJ Web Edition
    Info: Processing started: Sat Jun 02 11:06:23 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off UART -c UART
Warning: Using design file UART.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: UART-behav
    Info: Found entity 1: UART
Info: Elaborating entity "UART" for the top level hierarchy
Warning (10492): VHDL Process Statement warning at UART.vhd(46): signal "cs" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at UART.vhd(92): signal "cs" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at UART.vhd(124): signal "cs" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at UART.vhd(142): signal "cs" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at UART.vhd(172): signal "cs" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at UART.vhd(219): signal "cs" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info: Partition "Top" is synthesized because changes to the associated source files are detected
Info: Power-up level of register "t_shift[11]" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "t_shift[11]" with stuck data_in port to stuck value VCC
Info: Starting High-Level Optimization for Top Partition
Info: Power-up level of register "sst[0]" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "sst[0]" with stuck data_in port to stuck value VCC
Info: Starting High-Level Optimization for Top Partition
Info: Starting Logic Optimization and Technology Mapping for Top Partition
Info: Registers with preset signals will power-up high
Info: Implemented 129 device resources after synthesis - the final resource count might be different
    Info: Implemented 8 input pins
    Info: Implemented 4 output pins
    Info: Implemented 16 bidirectional pins
    Info: Implemented 101 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 9 warnings
    Info: Processing ended: Sat Jun 02 11:06:28 2007
    Info: Elapsed time: 00:00:06