senduard.map.qmsg

利用VHDL实现CPLD（EPM240T100C5）的串口发送程序

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Nov 25 18:54:33 2007 " "Info: Processing started: Sun Nov 25 18:54:33 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --lower_priority --read_settings_files=on --write_settings_files=off senduard -c senduard " "Info: Command: quartus_map --lower_priority --read_settings_files=on --write_settings_files=off senduard -c senduard" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "senduard.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file senduard.v" { { "Info" "ISGN_ENTITY_NAME" "1 senduard " "Info: Found entity 1: senduard" {  } { { "senduard.v" "" { Text "F:/CPLD-FPGA/dboard V2/firmware/verilog/senduard_50m/senduard.v" 23 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "senduard " "Info: Elaborating entity \"senduard\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 senduard.v(73) " "Warning (10230): Verilog HDL assignment warning at senduard.v(73): truncated value with size 32 to match size of target (8)" {  } { { "senduard.v" "" { Text "F:/CPLD-FPGA/dboard V2/firmware/verilog/senduard_50m/senduard.v" 73 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 senduard.v(125) " "Warning (10230): Verilog HDL assignment warning at senduard.v(125): truncated value with size 32 to match size of target (4)" {  } { { "senduard.v" "" { Text "F:/CPLD-FPGA/dboard V2/firmware/verilog/senduard_50m/senduard.v" 125 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 senduard.v(178) " "Warning (10230): Verilog HDL assignment warning at senduard.v(178): truncated value with size 32 to match size of target (4)" {  } { { "senduard.v" "" { Text "F:/CPLD-FPGA/dboard V2/firmware/verilog/senduard_50m/senduard.v" 178 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Info" "IFTM_FTM_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "senduard.v" "" { Text "F:/CPLD-FPGA/dboard V2/firmware/verilog/senduard_50m/senduard.v" 26 -1 0 } } { "senduard.v" "" { Text "F:/CPLD-FPGA/dboard V2/firmware/verilog/senduard_50m/senduard.v" 27 -1 0 } } { "senduard.v" "" { Text "F:/CPLD-FPGA/dboard V2/firmware/verilog/senduard_50m/senduard.v" 46 -1 0 } } { "senduard.v" "" { Text "F:/CPLD-FPGA/dboard V2/firmware/verilog/senduard_50m/senduard.v" 47 -1 0 } }  } 0 0 "Registers with preset signals will power-up high" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "83 " "Info: Implemented 83 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "11 " "Info: Implemented 11 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "11 " "Info: Implemented 11 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "61 " "Info: Implemented 61 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 3 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Nov 25 18:54:38 2007 " "Info: Processing ended: Sun Nov 25 18:54:38 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Info: Elapsed time: 00:00:06" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}