svga_timing_generation.v

利用VHDL实现CPLD（EPM240T100C5）的VGA屏幕输出

/*
-------------------------------------------------------------------------------
   Title      : SVGA Video Controller
   Project    : VGA TEST
-------------------------------------------------------------------------------
   File       : SVGA_TIMING_GENERATION.v
   Company    : Think Studio.
   Created    : 2006/06/20
   Last Update: 2006/06/20
   Copyright  : Think Studio, 2006
-------------------------------------------------------------------------------
   Uses       : svga_defines.v
-------------------------------------------------------------------------------
   Used by    : SVGA_CTRL.v
-------------------------------------------------------------------------------
   Description: This module creates the timing and control signals for the 
		MicroBlaze SVGA output. The module provides character-mapped addressing
	 	in addition to the control signals for the DAC and the VGA output connector. 
		The design supports screen resolutions up to 1024 x 768. The user will have
	 	to add the charcater memory RAM and the character generator ROM and create
	 	the required pixel clock.

		The video mode used is defined in the svga_defines.v file.

	Conventions:
		All external port signals are UPPER CASE.
		Active HIGH PORT signals have a P suffex
		Active LOW PORT signals have a N suffex.
		All internal signals are LOWER CASE and are active HIGH.

-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
*/



`include "svga_defines.v"

module vgatest (
pixel_clock50,
reset,
h_synch,
v_synch,
R,
G,
B
);

input 			pixel_clock50;	// pixel clock 
input 			reset;			// reset
output 			h_synch;	// horizontal synch for VGA connector
output 			v_synch;	// vertical synch for VGA connector
output[1:0] 			R,G,B;

reg [9:0]		line_count;		// counts the display lines
reg [10:0]		pixel_count;	// counts the pixels in a line	
reg				h_synch;		// horizontal synch
reg				v_synch;		// vertical synch
reg	[1:0]				R,G,B;
reg pixel_clock;

always @(posedge pixel_clock50)
begin
	pixel_clock <= !pixel_clock;
end
// CREATE THE HORIZONTAL LINE PIXEL COUNTER
always @ (posedge pixel_clock or posedge reset) begin
	if (reset)
 		begin						// on reset set pixel counter to 0
			pixel_count <= 11'h000;
		end

	else if (pixel_count == (`H_TOTAL - 1))
 		begin							// last pixel in the line
			pixel_count <= 11'h000;		// reset pixel counter
		end

	else 	begin
			pixel_count <= pixel_count +1;		
		end
	end

// CREATE THE HORIZONTAL SYNCH PULSE
always @ (posedge pixel_clock or posedge reset) begin
	if (reset)
 		begin						// on reset
			h_synch <= 1'b0;		// remove h_synch
		end

	else if (pixel_count == (`H_ACTIVE + `H_FRONT_PORCH -1)) 
	  	begin					// start of h_synch
			h_synch <= 1'b1;
		end

	else if (pixel_count == (`H_TOTAL - `H_BACK_PORCH -1))
 	 	begin					// end of h_synch
			h_synch <= 1'b0;
		end
	end


// CREATE THE VERTICAL FRAME LINE COUNTER
always @ (posedge pixel_clock or posedge reset) begin
	if (reset)
 		begin							// on reset set line counter to 0
			line_count <= 10'h000;
		end

	else if ((line_count == (`V_TOTAL - 1))&& (pixel_count == (`H_TOTAL - 1)))
		begin							// last pixel in last line of frame 
			line_count <= 10'h000;		// reset line counter
		end

	else if ((pixel_count == (`H_TOTAL - 1)))
		begin							// last pixel but not last line
			line_count <= line_count + 1;// increment line counter
		end
	end

// CREATE THE VERTICAL SYNCH PULSE
always @ (posedge pixel_clock or posedge reset) begin
	if (reset)
 		begin							// on reset
			v_synch = 1'b0;				// remove v_synch
		end

	else if ((line_count == (`V_ACTIVE + `V_FRONT_PORCH -1) &&
		   (pixel_count == `H_TOTAL - 1))) 
	  	begin							// start of v_synch
			v_synch = 1'b1;
		end
	
	else if ((line_count == (`V_TOTAL - `V_BACK_PORCH - 1))	&&
		   (pixel_count == (`H_TOTAL - 1)))
	 	begin							// end of v_synch
			v_synch = 1'b0;
		end
	end

always @ (posedge pixel_clock) begin
	case (pixel_count)
		1 :
		begin
			R <= 2'b11;
			G <= 2'b00;
			B <= 2'b00;
		end
		`H_ACTIVE/16 :
		begin
			R <= 2'b00;
			G <= 2'b11;
			B <= 2'b00;
		end
		`H_ACTIVE/8 :
		begin
			R <= 2'b00;
			G <= 2'b00;
			B <= 2'b11;
		end
		`H_ACTIVE*3/16 :
		begin
			R <= 2'b11;
			G <= 2'b11;
			B <= 2'b00;
		end
		`H_ACTIVE/4 :
		begin
			R <= 2'b11;
			G <= 2'b00;
			B <= 2'b11;
		end
		`H_ACTIVE*5/16 :
		begin
			R <= 2'b00;
			G <= 2'b11;
			B <= 2'b11;
		end
		`H_ACTIVE*3/8 :
		begin
			R <= 2'b11;
			G <= 2'b11;
			B <= 2'b11;
		end
		`H_ACTIVE*7/16 :
		begin
			R <= 2'b10;
			G <= 2'b00;
			B <= 2'b00;
		end
		`H_ACTIVE/2 :
		begin
			R <= 2'b01;
			G <= 2'b00;
			B <= 2'b00;
		end
		`H_ACTIVE*9/16 :
		begin
			R <= 2'b00;
			G <= 2'b10;
			B <= 2'b00;
		end
		`H_ACTIVE*5/8 :
		begin
			R <= 2'b00;
			G <= 2'b01;
			B <= 2'b00;
		end
		`H_ACTIVE*11/16 :
		begin
			R <= 2'b00;
			G <= 2'b00;
			B <= 2'b10;
		end
		`H_ACTIVE*3/4 :
		begin
			R <= 2'b00;
			G <= 2'b00;
			B <= 2'b01;
		end
		`H_ACTIVE*13/16 :
		begin
			R <= 2'b10;
			G <= 2'b10;
			B <= 2'b10;
		end
		`H_ACTIVE*7/8 :
		begin
			R <= 2'b01;
			G <= 2'b01;
			B <= 2'b01;
		end
		`H_ACTIVE*15/16 :
		begin
			R <= 2'b0;
			G <= 2'b0;
			B <= 2'b0;
		end
		default :
		begin
			R <= R;
			G <= G;
			B <= B;
		end
	endcase

end


endmodule //SVGA_TIMING_GENERATION