📄 vgatest.fit.rpt
字号:
; 8 ; 1 ;
; 9 ; 2 ;
; 10 ; 4 ;
+--------------------------------------------+------------------------------+
+-------------------------------------------------------------------+
; LAB-wide Signals ;
+------------------------------------+------------------------------+
; LAB-wide Signals (Average = 1.15) ; Number of LABs (Total = 13) ;
+------------------------------------+------------------------------+
; 1 Async. clear ; 6 ;
; 1 Clock ; 9 ;
+------------------------------------+------------------------------+
+----------------------------------------------------------------------------+
; LAB Signals Sourced ;
+---------------------------------------------+------------------------------+
; Number of Signals Sourced (Average = 7.85) ; Number of LABs (Total = 13) ;
+---------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 1 ;
; 2 ; 1 ;
; 3 ; 0 ;
; 4 ; 1 ;
; 5 ; 1 ;
; 6 ; 2 ;
; 7 ; 0 ;
; 8 ; 1 ;
; 9 ; 1 ;
; 10 ; 2 ;
; 11 ; 0 ;
; 12 ; 1 ;
; 13 ; 1 ;
; 14 ; 0 ;
; 15 ; 0 ;
; 16 ; 1 ;
+---------------------------------------------+------------------------------+
+--------------------------------------------------------------------------------+
; LAB Signals Sourced Out ;
+-------------------------------------------------+------------------------------+
; Number of Signals Sourced Out (Average = 6.15) ; Number of LABs (Total = 13) ;
+-------------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 1 ;
; 2 ; 1 ;
; 3 ; 0 ;
; 4 ; 3 ;
; 5 ; 2 ;
; 6 ; 2 ;
; 7 ; 0 ;
; 8 ; 0 ;
; 9 ; 0 ;
; 10 ; 2 ;
; 11 ; 1 ;
; 12 ; 1 ;
+-------------------------------------------------+------------------------------+
+-----------------------------------------------------------------------------+
; LAB Distinct Inputs ;
+----------------------------------------------+------------------------------+
; Number of Distinct Inputs (Average = 11.92) ; Number of LABs (Total = 13) ;
+----------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 0 ;
; 3 ; 0 ;
; 4 ; 1 ;
; 5 ; 0 ;
; 6 ; 2 ;
; 7 ; 1 ;
; 8 ; 0 ;
; 9 ; 1 ;
; 10 ; 0 ;
; 11 ; 2 ;
; 12 ; 1 ;
; 13 ; 0 ;
; 14 ; 0 ;
; 15 ; 1 ;
; 16 ; 0 ;
; 17 ; 1 ;
; 18 ; 2 ;
; 19 ; 0 ;
; 20 ; 0 ;
; 21 ; 1 ;
+----------------------------------------------+------------------------------+
+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
Info: Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version
Info: Processing started: Fri Jun 01 13:41:45 2007
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off vgatest -c vgatest
Info: Selected device EPM240T100C5 for design "vgatest"
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices.
Info: Device EPM240T100I5 is compatible
Info: Device EPM570T100C5 is compatible
Info: Device EPM570T100I5 is compatible
Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
Info: Assuming a global fmax requirement of 1000 MHz
Info: Assuming a global tsu requirement of 2.0 ns
Info: Assuming a global tco requirement of 1.0 ns
Info: Assuming a global tpd requirement of 1.0 ns
Info: Performing register packing on registers with non-logic cell location assignments
Info: Completed register packing on registers with non-logic cell location assignments
Info: Completed User Assigned Global Signals Promotion Operation
Info: Automatically promoted some destinations of signal "pixel_clock" to use Global clock
Info: Destination "pixel_clock" may be non-global or may not use global clock
Info: Automatically promoted signal "reset" to use Global clock
Info: Pin "reset" drives global clock, but is not placed in a dedicated clock pin position
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Moving registers into LUTs to improve timing and density
Info: Started processing fast register assignments
Info: Finished processing fast register assignments
Info: Finished moving registers into LUTs
Info: Finished register packing
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Estimated most critical path is register to register delay of 11.171 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X5_Y4; Fanout = 9; REG Node = 'pixel_count[9]'
Info: 2: + IC(1.700 ns) + CELL(0.914 ns) = 2.614 ns; Loc. = LAB_X3_Y4; Fanout = 1; COMB Node = 'pixel_count[0]~434'
Info: 3: + IC(0.344 ns) + CELL(0.914 ns) = 3.872 ns; Loc. = LAB_X3_Y4; Fanout = 6; COMB Node = 'pixel_count[0]~435'
Info: 4: + IC(0.671 ns) + CELL(0.511 ns) = 5.054 ns; Loc. = LAB_X3_Y4; Fanout = 4; COMB Node = 'reduce_nor~2840'
Info: 5: + IC(1.230 ns) + CELL(0.978 ns) = 7.262 ns; Loc. = LAB_X4_Y4; Fanout = 2; COMB Node = 'add~414'
Info: 6: + IC(0.000 ns) + CELL(0.123 ns) = 7.385 ns; Loc. = LAB_X4_Y4; Fanout = 2; COMB Node = 'add~374'
Info: 7: + IC(0.000 ns) + CELL(0.123 ns) = 7.508 ns; Loc. = LAB_X4_Y4; Fanout = 2; COMB Node = 'add~419'
Info: 8: + IC(0.000 ns) + CELL(0.123 ns) = 7.631 ns; Loc. = LAB_X4_Y4; Fanout = 2; COMB Node = 'add~379'
Info: 9: + IC(0.000 ns) + CELL(0.399 ns) = 8.030 ns; Loc. = LAB_X4_Y4; Fanout = 5; COMB Node = 'add~384'
Info: 10: + IC(0.000 ns) + CELL(1.234 ns) = 9.264 ns; Loc. = LAB_X4_Y4; Fanout = 1; COMB Node = 'add~397'
Info: 11: + IC(0.724 ns) + CELL(1.183 ns) = 11.171 ns; Loc. = LAB_X5_Y4; Fanout = 5; REG Node = 'line_count[6]'
Info: Total cell delay = 6.502 ns ( 58.20 % )
Info: Total interconnect delay = 4.669 ns ( 41.80 % )
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Fitter routing operations beginning
Info: Fitter routing operations ending: elapsed time is 00:00:00
Info: Fitter performed an Auto Fit compilation. No optimizations were skipped because the design's timing and/or routability requirements required full optimization
Info: Quartus II Fitter was successful. 0 errors, 0 warnings
Info: Processing ended: Fri Jun 01 13:41:49 2007
Info: Elapsed time: 00:00:04
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