vgatest.tan.summary

利用VHDL实现CPLD（EPM240T100C5）的VGA屏幕输出

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Timing Analyzer Summary
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Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 12.096 ns
From           : R[0]~reg0
To             : R[0]
From Clock     : pixel_clock50
To Clock       : 
Failed Paths   : 0

Type           : Clock Setup: 'pixel_clock50'
Slack          : N/A
Required Time  : None
Actual Time    : 92.77 MHz ( period = 10.779 ns )
From           : pixel_count[1]
To             : R[1]~reg0
From Clock     : pixel_clock50
To Clock       : pixel_clock50
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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