vgatest.map.qmsg

利用VHDL实现CPLD（EPM240T100C5）的VGA屏幕输出

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version " "Info: Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Jun 01 13:41:41 2007 " "Info: Processing started: Fri Jun 01 13:41:41 2007" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off vgatest -c vgatest " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off vgatest -c vgatest" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "svga_defines.v 0 0 " "Info: Found 0 design units, including 0 entities, in source file svga_defines.v" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "SVGA_TIMING_GENERATION.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file SVGA_TIMING_GENERATION.v" { { "Info" "ISGN_ENTITY_NAME" "1 vgatest " "Info: Found entity 1: vgatest" {  } { { "SVGA_TIMING_GENERATION.v" "" { Text "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/SVGA_TIMING_GENERATION.v" 39 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "vgatest " "Info: Elaborating entity \"vgatest\" for the top level hierarchy" {  } {  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 11 SVGA_TIMING_GENERATION.v(79) " "Warning: Verilog HDL assignment warning at SVGA_TIMING_GENERATION.v(79): truncated value with size 32 to match size of target (11)" {  } { { "SVGA_TIMING_GENERATION.v" "" { Text "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/SVGA_TIMING_GENERATION.v" 79 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 SVGA_TIMING_GENERATION.v(116) " "Warning: Verilog HDL assignment warning at SVGA_TIMING_GENERATION.v(116): truncated value with size 32 to match size of target (10)" {  } { { "SVGA_TIMING_GENERATION.v" "" { Text "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/SVGA_TIMING_GENERATION.v" 116 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 11 SVGA_TIMING_GENERATION.v(142) " "Warning: (10271) Verilog HDL Case Statement warning at SVGA_TIMING_GENERATION.v(142): size of case item expression (32) exceeds the size of the case expression (11)" {  } { { "SVGA_TIMING_GENERATION.v" "" { Text "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/SVGA_TIMING_GENERATION.v" 142 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 11 SVGA_TIMING_GENERATION.v(148) " "Warning: (10271) Verilog HDL Case Statement warning at SVGA_TIMING_GENERATION.v(148): size of case item expression (32) exceeds the size of the case expression (11)" {  } { { "SVGA_TIMING_GENERATION.v" "" { Text "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/SVGA_TIMING_GENERATION.v" 148 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 11 SVGA_TIMING_GENERATION.v(154) " "Warning: (10271) Verilog HDL Case Statement warning at SVGA_TIMING_GENERATION.v(154): size of case item expression (32) exceeds the size of the case expression (11)" {  } { { "SVGA_TIMING_GENERATION.v" "" { Text "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/SVGA_TIMING_GENERATION.v" 154 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 11 SVGA_TIMING_GENERATION.v(160) " "Warning: (10271) Verilog HDL Case Statement warning at SVGA_TIMING_GENERATION.v(160): size of case item expression (32) exceeds the size of the case expression (11)" {  } { { "SVGA_TIMING_GENERATION.v" "" { Text "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/SVGA_TIMING_GENERATION.v" 160 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 11 SVGA_TIMING_GENERATION.v(166) " "Warning: (10271) Verilog HDL Case Statement warning at SVGA_TIMING_GENERATION.v(166): size of case item expression (32) exceeds the size of the case expression (11)" {  } { { "SVGA_TIMING_GENERATION.v" "" { Text "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/SVGA_TIMING_GENERATION.v" 166 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 11 SVGA_TIMING_GENERATION.v(172) " "Warning: (10271) Verilog HDL Case Statement warning at SVGA_TIMING_GENERATION.v(172): size of case item expression (32) exceeds the size of the case expression (11)" {  } { { "SVGA_TIMING_GENERATION.v" "" { Text "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/SVGA_TIMING_GENERATION.v" 172 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 11 SVGA_TIMING_GENERATION.v(178) " "Warning: (10271) Verilog HDL Case Statement warning at SVGA_TIMING_GENERATION.v(178): size of case item expression (32) exceeds the size of the case expression (11)" {  } { { "SVGA_TIMING_GENERATION.v" "" { Text "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/SVGA_TIMING_GENERATION.v" 178 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 11 SVGA_TIMING_GENERATION.v(184) " "Warning: (10271) Verilog HDL Case Statement warning at SVGA_TIMING_GENERATION.v(184): size of case item expression (32) exceeds the size of the case expression (11)" {  } { { "SVGA_TIMING_GENERATION.v" "" { Text "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/SVGA_TIMING_GENERATION.v" 184 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 11 SVGA_TIMING_GENERATION.v(190) " "Warning: (10271) Verilog HDL Case Statement warning at SVGA_TIMING_GENERATION.v(190): size of case item expression (32) exceeds the size of the case expression (11)" {  } { { "SVGA_TIMING_GENERATION.v" "" { Text "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/SVGA_TIMING_GENERATION.v" 190 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 11 SVGA_TIMING_GENERATION.v(196) " "Warning: (10271) Verilog HDL Case Statement warning at SVGA_TIMING_GENERATION.v(196): size of case item expression (32) exceeds the size of the case expression (11)" {  } { { "SVGA_TIMING_GENERATION.v" "" { Text "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/SVGA_TIMING_GENERATION.v" 196 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 11 SVGA_TIMING_GENERATION.v(202) " "Warning: (10271) Verilog HDL Case Statement warning at SVGA_TIMING_GENERATION.v(202): size of case item expression (32) exceeds the size of the case expression (11)" {  } { { "SVGA_TIMING_GENERATION.v" "" { Text "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/SVGA_TIMING_GENERATION.v" 202 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 11 SVGA_TIMING_GENERATION.v(208) " "Warning: (10271) Verilog HDL Case Statement warning at SVGA_TIMING_GENERATION.v(208): size of case item expression (32) exceeds the size of the case expression (11)" {  } { { "SVGA_TIMING_GENERATION.v" "" { Text "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/SVGA_TIMING_GENERATION.v" 208 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 11 SVGA_TIMING_GENERATION.v(214) " "Warning: (10271) Verilog HDL Case Statement warning at SVGA_TIMING_GENERATION.v(214): size of case item expression (32) exceeds the size of the case expression (11)" {  } { { "SVGA_TIMING_GENERATION.v" "" { Text "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/SVGA_TIMING_GENERATION.v" 214 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 11 SVGA_TIMING_GENERATION.v(220) " "Warning: (10271) Verilog HDL Case Statement warning at SVGA_TIMING_GENERATION.v(220): size of case item expression (32) exceeds the size of the case expression (11)" {  } { { "SVGA_TIMING_GENERATION.v" "" { Text "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/SVGA_TIMING_GENERATION.v" 220 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 11 SVGA_TIMING_GENERATION.v(226) " "Warning: (10271) Verilog HDL Case Statement warning at SVGA_TIMING_GENERATION.v(226): size of case item expression (32) exceeds the size of the case expression (11)" {  } { { "SVGA_TIMING_GENERATION.v" "" { Text "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/SVGA_TIMING_GENERATION.v" 226 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 11 SVGA_TIMING_GENERATION.v(232) " "Warning: (10271) Verilog HDL Case Statement warning at SVGA_TIMING_GENERATION.v(232): size of case item expression (32) exceeds the size of the case expression (11)" {  } { { "SVGA_TIMING_GENERATION.v" "" { Text "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/SVGA_TIMING_GENERATION.v" 232 0 0 } }  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "112 " "Info: Implemented 112 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "2 " "Info: Implemented 2 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "8 " "Info: Implemented 8 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "102 " "Info: Implemented 102 logic cells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 18 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 18 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Jun 01 13:41:44 2007 " "Info: Processing ended: Fri Jun 01 13:41:44 2007" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0}  } {  } 0}