vgatest.tan.qmsg

利用VHDL实现CPLD（EPM240T100C5）的VGA屏幕输出

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "pixel_clock " "Info: Detected ripple clock \"pixel_clock\" as buffer" {  } { { "SVGA_TIMING_GENERATION.v" "" { Text "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/SVGA_TIMING_GENERATION.v" 60 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "pixel_clock" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "pixel_clock50 register pixel_count\[1\] register R\[1\]~reg0 92.77 MHz 10.779 ns Internal " "Info: Clock \"pixel_clock50\" has Internal fmax of 92.77 MHz between source register \"pixel_count\[1\]\" and destination register \"R\[1\]~reg0\" (period= 10.779 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.070 ns + Longest register register " "Info: + Longest register to register delay is 10.070 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pixel_count\[1\] 1 REG LC_X3_Y4_N6 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X3_Y4_N6; Fanout = 6; REG Node = 'pixel_count\[1\]'" {  } { { "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/db/vgatest_cmp.qrpt" "" { Report "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/db/vgatest_cmp.qrpt" Compiler "vgatest" "UNKNOWN" "V1" "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/db/vgatest.quartus_db" { Floorplan "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/" "" "" { pixel_count[1] } "NODE_NAME" } "" } } { "SVGA_TIMING_GENERATION.v" "" { Text "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/SVGA_TIMING_GENERATION.v" 56 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.361 ns) + CELL(0.914 ns) 2.275 ns reduce_nor~2844 2 COMB LC_X2_Y4_N2 3 " "Info: 2: + IC(1.361 ns) + CELL(0.914 ns) = 2.275 ns; Loc. = LC_X2_Y4_N2; Fanout = 3; COMB Node = 'reduce_nor~2844'" {  } { { "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/db/vgatest_cmp.qrpt" "" { Report "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/db/vgatest_cmp.qrpt" Compiler "vgatest" "UNKNOWN" "V1" "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/db/vgatest.quartus_db" { Floorplan "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/" "" "2.275 ns" { pixel_count[1] reduce_nor~2844 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.772 ns) + CELL(0.200 ns) 3.247 ns reduce_nor~2845 3 COMB LC_X2_Y4_N8 3 " "Info: 3: + IC(0.772 ns) + CELL(0.200 ns) = 3.247 ns; Loc. = LC_X2_Y4_N8; Fanout = 3; COMB Node = 'reduce_nor~2845'" {  } { { "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/db/vgatest_cmp.qrpt" "" { Report "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/db/vgatest_cmp.qrpt" Compiler "vgatest" "UNKNOWN" "V1" "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/db/vgatest.quartus_db" { Floorplan "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/" "" "0.972 ns" { reduce_nor~2844 reduce_nor~2845 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.305 ns) + CELL(0.200 ns) 3.752 ns reduce_nor~2846 4 COMB LC_X2_Y4_N9 2 " "Info: 4: + IC(0.305 ns) + CELL(0.200 ns) = 3.752 ns; Loc. = LC_X2_Y4_N9; Fanout = 2; COMB Node = 'reduce_nor~2846'" {  } { { "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/db/vgatest_cmp.qrpt" "" { Report "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/db/vgatest_cmp.qrpt" Compiler "vgatest" "UNKNOWN" "V1" "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/db/vgatest.quartus_db" { Floorplan "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/" "" "0.505 ns" { reduce_nor~2845 reduce_nor~2846 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.471 ns) + CELL(0.200 ns) 6.423 ns reduce_nor~19 5 COMB LC_X7_Y4_N1 3 " "Info: 5: + IC(2.471 ns) + CELL(0.200 ns) = 6.423 ns; Loc. = LC_X7_Y4_N1; Fanout = 3; COMB Node = 'reduce_nor~19'" {  } { { "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/db/vgatest_cmp.qrpt" "" { Report "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/db/vgatest_cmp.qrpt" Compiler "vgatest" "UNKNOWN" "V1" "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/db/vgatest.quartus_db" { Floorplan "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/" "" "2.671 ns" { reduce_nor~2846 reduce_nor~19 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.729 ns) + CELL(0.200 ns) 7.352 ns Select~562 6 COMB LC_X7_Y4_N0 1 " "Info: 6: + IC(0.729 ns) + CELL(0.200 ns) = 7.352 ns; Loc. = LC_X7_Y4_N0; Fanout = 1; COMB Node = 'Select~562'" {  } { { "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/db/vgatest_cmp.qrpt" "" { Report "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/db/vgatest_cmp.qrpt" Compiler "vgatest" "UNKNOWN" "V1" "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/db/vgatest.quartus_db" { Floorplan "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/" "" "0.929 ns" { reduce_nor~19 Select~562 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.914 ns) + CELL(0.804 ns) 10.070 ns R\[1\]~reg0 7 REG LC_X7_Y3_N5 2 " "Info: 7: + IC(1.914 ns) + CELL(0.804 ns) = 10.070 ns; Loc. = LC_X7_Y3_N5; Fanout = 2; REG Node = 'R\[1\]~reg0'" {  } { { "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/db/vgatest_cmp.qrpt" "" { Report "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/db/vgatest_cmp.qrpt" Compiler "vgatest" "UNKNOWN" "V1" "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/db/vgatest.quartus_db" { Floorplan "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/" "" "2.718 ns" { Select~562 R[1]~reg0 } "NODE_NAME" } "" } } { "SVGA_TIMING_GENERATION.v" "" { Text "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/SVGA_TIMING_GENERATION.v" 246 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.518 ns 25.00 % " "Info: Total cell delay = 2.518 ns ( 25.00 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.552 ns 75.00 % " "Info: Total interconnect delay = 7.552 ns ( 75.00 % )" {  } {  } 0}  } { { "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/db/vgatest_cmp.qrpt" "" { Report "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/db/vgatest_cmp.qrpt" Compiler "vgatest" "UNKNOWN" "V1" "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/db/vgatest.quartus_db" { Floorplan "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/" "" "10.070 ns" { pixel_count[1] reduce_nor~2844 reduce_nor~2845 reduce_nor~2846 reduce_nor~19 Select~562 R[1]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "10.070 ns" { pixel_count[1] reduce_nor~2844 reduce_nor~2845 reduce_nor~2846 reduce_nor~19 Select~562 R[1]~reg0 } { 0.000ns 1.361ns 0.772ns 0.305ns 2.471ns 0.729ns 1.914ns } { 0.000ns 0.914ns 0.200ns 0.200ns 0.200ns 0.200ns 0.804ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pixel_clock50 destination 7.298 ns + Shortest register " "Info: + Shortest clock path from clock \"pixel_clock50\" to destination register is 7.298 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns pixel_clock50 1 CLK PIN_12 1 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 1; CLK Node = 'pixel_clock50'" {  } { { "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/db/vgatest_cmp.qrpt" "" { Report "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/db/vgatest_cmp.qrpt" Compiler "vgatest" "UNKNOWN" "V1" "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/db/vgatest.quartus_db" { Floorplan "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/" "" "" { pixel_clock50 } "NODE_NAME" } "" } } { "SVGA_TIMING_GENERATION.v" "" { Text "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/SVGA_TIMING_GENERATION.v" 49 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.177 ns) + CELL(1.294 ns) 3.634 ns pixel_clock 2 REG LC_X2_Y3_N4 30 " "Info: 2: + IC(1.177 ns) + CELL(1.294 ns) = 3.634 ns; Loc. = LC_X2_Y3_N4; Fanout = 30; REG Node = 'pixel_clock'" {  } { { "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/db/vgatest_cmp.qrpt" "" { Report "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/db/vgatest_cmp.qrpt" Compiler "vgatest" "UNKNOWN" "V1" "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/db/vgatest.quartus_db" { Floorplan "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/" "" "2.471 ns" { pixel_clock50 pixel_clock } "NODE_NAME" } "" } } { "SVGA_TIMING_GENERATION.v" "" { Text "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/SVGA_TIMING_GENERATION.v" 60 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.746 ns) + CELL(0.918 ns) 7.298 ns R\[1\]~reg0 3 REG LC_X7_Y3_N5 2 " "Info: 3: + IC(2.746 ns) + CELL(0.918 ns) = 7.298 ns; Loc. = LC_X7_Y3_N5; Fanout = 2; REG Node = 'R\[1\]~reg0'" {  } { { "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/db/vgatest_cmp.qrpt" "" { Report "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/db/vgatest_cmp.qrpt" Compiler "vgatest" "UNKNOWN" "V1" "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/db/vgatest.quartus_db" { Floorplan "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/" "" "3.664 ns" { pixel_clock R[1]~reg0 } "NODE_NAME" } "" } } { "SVGA_TIMING_GENERATION.v" "" { Text "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/SVGA_TIMING_GENERATION.v" 246 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.375 ns 46.25 % " "Info: Total cell delay = 3.375 ns ( 46.25 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.923 ns 53.75 % " "Info: Total interconnect delay = 3.923 ns ( 53.75 % )" {  } {  } 0}  } { { "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/db/vgatest_cmp.qrpt" "" { Report "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/db/vgatest_cmp.qrpt" Compiler "vgatest" "UNKNOWN" "V1" "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/db/vgatest.quartus_db" { Floorplan "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/" "" "7.298 ns" { pixel_clock50 pixel_clock R[1]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "7.298 ns" { pixel_clock50 pixel_clock50~combout pixel_clock R[1]~reg0 } { 0.000ns 0.000ns 1.177ns 2.746ns } { 0.000ns 1.163ns 1.294ns 0.918ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pixel_clock50 source 7.298 ns - Longest register " "Info: - Longest clock path from clock \"pixel_clock50\" to source register is 7.298 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns pixel_clock50 1 CLK PIN_12 1 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 1; CLK Node = 'pixel_clock50'" {  } { { "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/db/vgatest_cmp.qrpt" "" { Report "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/db/vgatest_cmp.qrpt" Compiler "vgatest" "UNKNOWN" "V1" "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/db/vgatest.quartus_db" { Floorplan "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/" "" "" { pixel_clock50 } "NODE_NAME" } "" } } { "SVGA_TIMING_GENERATION.v" "" { Text "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/SVGA_TIMING_GENERATION.v" 49 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.177 ns) + CELL(1.294 ns) 3.634 ns pixel_clock 2 REG LC_X2_Y3_N4 30 " "Info: 2: + IC(1.177 ns) + CELL(1.294 ns) = 3.634 ns; Loc. = LC_X2_Y3_N4; Fanout = 30; REG Node = 'pixel_clock'" {  } { { "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/db/vgatest_cmp.qrpt" "" { Report "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/db/vgatest_cmp.qrpt" Compiler "vgatest" "UNKNOWN" "V1" "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/db/vgatest.quartus_db" { Floorplan "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/" "" "2.471 ns" { pixel_clock50 pixel_clock } "NODE_NAME" } "" } } { "SVGA_TIMING_GENERATION.v" "" { Text "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/SVGA_TIMING_GENERATION.v" 60 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.746 ns) + CELL(0.918 ns) 7.298 ns pixel_count\[1\] 3 REG LC_X3_Y4_N6 6 " "Info: 3: + IC(2.746 ns) + CELL(0.918 ns) = 7.298 ns; Loc. = LC_X3_Y4_N6; Fanout = 6; REG Node = 'pixel_count\[1\]'" {  } { { "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/db/vgatest_cmp.qrpt" "" { Report "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/db/vgatest_cmp.qrpt" Compiler "vgatest" "UNKNOWN" "V1" "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/db/vgatest.quartus_db" { Floorplan "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/" "" "3.664 ns" { pixel_clock pixel_count[1] } "NODE_NAME" } "" } } { "SVGA_TIMING_GENERATION.v" "" { Text "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/SVGA_TIMING_GENERATION.v" 56 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.375 ns 46.25 % " "Info: Total cell delay = 3.375 ns ( 46.25 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.923 ns 53.75 % " "Info: Total interconnect delay = 3.923 ns ( 53.75 % )" {  } {  } 0}  } { { "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/db/vgatest_cmp.qrpt" "" { Report "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/db/vgatest_cmp.qrpt" Compiler "vgatest" "UNKNOWN" "V1" "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/db/vgatest.quartus_db" { Floorplan "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/" "" "7.298 ns" { pixel_clock50 pixel_clock pixel_count[1] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "7.298 ns" { pixel_clock50 pixel_clock50~combout pixel_clock pixel_count[1] } { 0.000ns 0.000ns 1.177ns 2.746ns } { 0.000ns 1.163ns 1.294ns 0.918ns } } }  } 0}  } { { "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/db/vgatest_cmp.qrpt" "" { Report "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/db/vgatest_cmp.qrpt" Compiler "vgatest" "UNKNOWN" "V1" "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/db/vgatest.quartus_db" { Floorplan "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/" "" "7.298 ns" { pixel_clock50 pixel_clock R[1]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "7.298 ns" { pixel_clock50 pixel_clock50~combout pixel_clock R[1]~reg0 } { 0.000ns 0.000ns 1.177ns 2.746ns } { 0.000ns 1.163ns 1.294ns 0.918ns } } } { "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/db/vgatest_cmp.qrpt" "" { Report "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/db/vgatest_cmp.qrpt" Compiler "vgatest" "UNKNOWN" "V1" "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/db/vgatest.quartus_db" { Floorplan "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/" "" "7.298 ns" { pixel_clock50 pixel_clock pixel_count[1] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "7.298 ns" { pixel_clock50 pixel_clock50~combout pixel_clock pixel_count[1] } { 0.000ns 0.000ns 1.177ns 2.746ns } { 0.000ns 1.163ns 1.294ns 0.918ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "SVGA_TIMING_GENERATION.v" "" { Text "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/SVGA_TIMING_GENERATION.v" 56 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "SVGA_TIMING_GENERATION.v" "" { Text "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/SVGA_TIMING_GENERATION.v" 246 -1 0 } }  } 0}  } { { "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/db/vgatest_cmp.qrpt" "" { Report "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/db/vgatest_cmp.qrpt" Compiler "vgatest" "UNKNOWN" "V1" "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/db/vgatest.quartus_db" { Floorplan "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/" "" "10.070 ns" { pixel_count[1] reduce_nor~2844 reduce_nor~2845 reduce_nor~2846 reduce_nor~19 Select~562 R[1]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "10.070 ns" { pixel_count[1] reduce_nor~2844 reduce_nor~2845 reduce_nor~2846 reduce_nor~19 Select~562 R[1]~reg0 } { 0.000ns 1.361ns 0.772ns 0.305ns 2.471ns 0.729ns 1.914ns } { 0.000ns 0.914ns 0.200ns 0.200ns 0.200ns 0.200ns 0.804ns } } } { "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/db/vgatest_cmp.qrpt" "" { Report "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/db/vgatest_cmp.qrpt" Compiler "vgatest" "UNKNOWN" "V1" "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/db/vgatest.quartus_db" { Floorplan "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/" "" "7.298 ns" { pixel_clock50 pixel_clock R[1]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "7.298 ns" { pixel_clock50 pixel_clock50~combout pixel_clock R[1]~reg0 } { 0.000ns 0.000ns 1.177ns 2.746ns } { 0.000ns 1.163ns 1.294ns 0.918ns } } } { "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/db/vgatest_cmp.qrpt" "" { Report "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/db/vgatest_cmp.qrpt" Compiler "vgatest" "UNKNOWN" "V1" "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/db/vgatest.quartus_db" { Floorplan "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/" "" "7.298 ns" { pixel_clock50 pixel_clock pixel_count[1] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "7.298 ns" { pixel_clock50 pixel_clock50~combout pixel_clock pixel_count[1] } { 0.000ns 0.000ns 1.177ns 2.746ns } { 0.000ns 1.163ns 1.294ns 0.918ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "pixel_clock50 R\[0\] R\[0\]~reg0 12.096 ns register " "Info: tco from clock \"pixel_clock50\" to destination pin \"R\[0\]\" through register \"R\[0\]~reg0\" is 12.096 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pixel_clock50 source 7.298 ns + Longest register " "Info: + Longest clock path from clock \"pixel_clock50\" to source register is 7.298 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns pixel_clock50 1 CLK PIN_12 1 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 1; CLK Node = 'pixel_clock50'" {  } { { "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/db/vgatest_cmp.qrpt" "" { Report "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/db/vgatest_cmp.qrpt" Compiler "vgatest" "UNKNOWN" "V1" "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/db/vgatest.quartus_db" { Floorplan "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/" "" "" { pixel_clock50 } "NODE_NAME" } "" } } { "SVGA_TIMING_GENERATION.v" "" { Text "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/SVGA_TIMING_GENERATION.v" 49 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.177 ns) + CELL(1.294 ns) 3.634 ns pixel_clock 2 REG LC_X2_Y3_N4 30 " "Info: 2: + IC(1.177 ns) + CELL(1.294 ns) = 3.634 ns; Loc. = LC_X2_Y3_N4; Fanout = 30; REG Node = 'pixel_clock'" {  } { { "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/db/vgatest_cmp.qrpt" "" { Report "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/db/vgatest_cmp.qrpt" Compiler "vgatest" "UNKNOWN" "V1" "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/db/vgatest.quartus_db" { Floorplan "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/" "" "2.471 ns" { pixel_clock50 pixel_clock } "NODE_NAME" } "" } } { "SVGA_TIMING_GENERATION.v" "" { Text "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/SVGA_TIMING_GENERATION.v" 60 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.746 ns) + CELL(0.918 ns) 7.298 ns R\[0\]~reg0 3 REG LC_X7_Y3_N3 2 " "Info: 3: + IC(2.746 ns) + CELL(0.918 ns) = 7.298 ns; Loc. = LC_X7_Y3_N3; Fanout = 2; REG Node = 'R\[0\]~reg0'" {  } { { "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/db/vgatest_cmp.qrpt" "" { Report "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/db/vgatest_cmp.qrpt" Compiler "vgatest" "UNKNOWN" "V1" "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/db/vgatest.quartus_db" { Floorplan "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/" "" "3.664 ns" { pixel_clock R[0]~reg0 } "NODE_NAME" } "" } } { "SVGA_TIMING_GENERATION.v" "" { Text "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/SVGA_TIMING_GENERATION.v" 246 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.375 ns 46.25 % " "Info: Total cell delay = 3.375 ns ( 46.25 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.923 ns 53.75 % " "Info: Total interconnect delay = 3.923 ns ( 53.75 % )" {  } {  } 0}  } { { "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/db/vgatest_cmp.qrpt" "" { Report "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/db/vgatest_cmp.qrpt" Compiler "vgatest" "UNKNOWN" "V1" "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/db/vgatest.quartus_db" { Floorplan "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/" "" "7.298 ns" { pixel_clock50 pixel_clock R[0]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "7.298 ns" { pixel_clock50 pixel_clock50~combout pixel_clock R[0]~reg0 } { 0.000ns 0.000ns 1.177ns 2.746ns } { 0.000ns 1.163ns 1.294ns 0.918ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "SVGA_TIMING_GENERATION.v" "" { Text "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/SVGA_TIMING_GENERATION.v" 246 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.422 ns + Longest register pin " "Info: + Longest register to pin delay is 4.422 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns R\[0\]~reg0 1 REG LC_X7_Y3_N3 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X7_Y3_N3; Fanout = 2; REG Node = 'R\[0\]~reg0'" {  } { { "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/db/vgatest_cmp.qrpt" "" { Report "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/db/vgatest_cmp.qrpt" Compiler "vgatest" "UNKNOWN" "V1" "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/db/vgatest.quartus_db" { Floorplan "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/" "" "" { R[0]~reg0 } "NODE_NAME" } "" } } { "SVGA_TIMING_GENERATION.v" "" { Text "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/SVGA_TIMING_GENERATION.v" 246 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.100 ns) + CELL(2.322 ns) 4.422 ns R\[0\] 2 PIN PIN_71 0 " "Info: 2: + IC(2.100 ns) + CELL(2.322 ns) = 4.422 ns; Loc. = PIN_71; Fanout = 0; PIN Node = 'R\[0\]'" {  } { { "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/db/vgatest_cmp.qrpt" "" { Report "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/db/vgatest_cmp.qrpt" Compiler "vgatest" "UNKNOWN" "V1" "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/db/vgatest.quartus_db" { Floorplan "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/" "" "4.422 ns" { R[0]~reg0 R[0] } "NODE_NAME" } "" } } { "SVGA_TIMING_GENERATION.v" "" { Text "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/SVGA_TIMING_GENERATION.v" 53 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.322 ns 52.51 % " "Info: Total cell delay = 2.322 ns ( 52.51 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.100 ns 47.49 % " "Info: Total interconnect delay = 2.100 ns ( 47.49 % )" {  } {  } 0}  } { { "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/db/vgatest_cmp.qrpt" "" { Report "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/db/vgatest_cmp.qrpt" Compiler "vgatest" "UNKNOWN" "V1" "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/db/vgatest.quartus_db" { Floorplan "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/" "" "4.422 ns" { R[0]~reg0 R[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "4.422 ns" { R[0]~reg0 R[0] } { 0.000ns 2.100ns } { 0.000ns 2.322ns } } }  } 0}  } { { "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/db/vgatest_cmp.qrpt" "" { Report "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/db/vgatest_cmp.qrpt" Compiler "vgatest" "UNKNOWN" "V1" "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/db/vgatest.quartus_db" { Floorplan "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/" "" "7.298 ns" { pixel_clock50 pixel_clock R[0]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "7.298 ns" { pixel_clock50 pixel_clock50~combout pixel_clock R[0]~reg0 } { 0.000ns 0.000ns 1.177ns 2.746ns } { 0.000ns 1.163ns 1.294ns 0.918ns } } } { "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/db/vgatest_cmp.qrpt" "" { Report "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/db/vgatest_cmp.qrpt" Compiler "vgatest" "UNKNOWN" "V1" "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/db/vgatest.quartus_db" { Floorplan "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/" "" "4.422 ns" { R[0]~reg0 R[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "4.422 ns" { R[0]~reg0 R[0] } { 0.000ns 2.100ns } { 0.000ns 2.322ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Jun 01 13:41:53 2007 " "Info: Processing ended: Fri Jun 01 13:41:53 2007" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}