vgatest.tan.qmsg

利用VHDL实现CPLD（EPM240T100C5）的VGA屏幕输出

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus II " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version " "Info: Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Jun 01 13:41:52 2007 " "Info: Processing started: Fri Jun 01 13:41:52 2007" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off vgatest -c vgatest " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off vgatest -c vgatest" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "pixel_clock50 " "Info: Assuming node \"pixel_clock50\" is an undefined clock" {  } { { "SVGA_TIMING_GENERATION.v" "" { Text "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/SVGA_TIMING_GENERATION.v" 49 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "pixel_clock50" } } } }  } 0}  } {  } 0}