vgatest.fit.qmsg

利用VHDL实现CPLD（EPM240T100C5）的VGA屏幕输出

{ "Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Info: Moving registers into LUTs to improve timing and density" {  } {  } 0}
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Info: Started processing fast register assignments" {  } {  } 0}
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Info: Finished processing fast register assignments" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "" "Info: Finished moving registers into LUTs" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "11.171 ns register register " "Info: Estimated most critical path is register to register delay of 11.171 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pixel_count\[9\] 1 REG LAB_X5_Y4 9 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X5_Y4; Fanout = 9; REG Node = 'pixel_count\[9\]'" {  } { { "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/db/vgatest_cmp.qrpt" "" { Report "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/db/vgatest_cmp.qrpt" Compiler "vgatest" "UNKNOWN" "V1" "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/db/vgatest.quartus_db" { Floorplan "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/" "" "" { pixel_count[9] } "NODE_NAME" } "" } } { "SVGA_TIMING_GENERATION.v" "" { Text "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/SVGA_TIMING_GENERATION.v" 56 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.700 ns) + CELL(0.914 ns) 2.614 ns pixel_count\[0\]~434 2 COMB LAB_X3_Y4 1 " "Info: 2: + IC(1.700 ns) + CELL(0.914 ns) = 2.614 ns; Loc. = LAB_X3_Y4; Fanout = 1; COMB Node = 'pixel_count\[0\]~434'" {  } { { "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/db/vgatest_cmp.qrpt" "" { Report "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/db/vgatest_cmp.qrpt" Compiler "vgatest" "UNKNOWN" "V1" "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/db/vgatest.quartus_db" { Floorplan "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/" "" "2.614 ns" { pixel_count[9] pixel_count[0]~434 } "NODE_NAME" } "" } } { "SVGA_TIMING_GENERATION.v" "" { Text "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/SVGA_TIMING_GENERATION.v" 56 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.344 ns) + CELL(0.914 ns) 3.872 ns pixel_count\[0\]~435 3 COMB LAB_X3_Y4 6 " "Info: 3: + IC(0.344 ns) + CELL(0.914 ns) = 3.872 ns; Loc. = LAB_X3_Y4; Fanout = 6; COMB Node = 'pixel_count\[0\]~435'" {  } { { "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/db/vgatest_cmp.qrpt" "" { Report "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/db/vgatest_cmp.qrpt" Compiler "vgatest" "UNKNOWN" "V1" "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/db/vgatest.quartus_db" { Floorplan "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/" "" "1.258 ns" { pixel_count[0]~434 pixel_count[0]~435 } "NODE_NAME" } "" } } { "SVGA_TIMING_GENERATION.v" "" { Text "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/SVGA_TIMING_GENERATION.v" 56 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.671 ns) + CELL(0.511 ns) 5.054 ns reduce_nor~2840 4 COMB LAB_X3_Y4 4 " "Info: 4: + IC(0.671 ns) + CELL(0.511 ns) = 5.054 ns; Loc. = LAB_X3_Y4; Fanout = 4; COMB Node = 'reduce_nor~2840'" {  } { { "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/db/vgatest_cmp.qrpt" "" { Report "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/db/vgatest_cmp.qrpt" Compiler "vgatest" "UNKNOWN" "V1" "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/db/vgatest.quartus_db" { Floorplan "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/" "" "1.182 ns" { pixel_count[0]~435 reduce_nor~2840 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.230 ns) + CELL(0.978 ns) 7.262 ns add~414 5 COMB LAB_X4_Y4 2 " "Info: 5: + IC(1.230 ns) + CELL(0.978 ns) = 7.262 ns; Loc. = LAB_X4_Y4; Fanout = 2; COMB Node = 'add~414'" {  } { { "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/db/vgatest_cmp.qrpt" "" { Report "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/db/vgatest_cmp.qrpt" Compiler "vgatest" "UNKNOWN" "V1" "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/db/vgatest.quartus_db" { Floorplan "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/" "" "2.208 ns" { reduce_nor~2840 add~414 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.123 ns) 7.385 ns add~374 6 COMB LAB_X4_Y4 2 " "Info: 6: + IC(0.000 ns) + CELL(0.123 ns) = 7.385 ns; Loc. = LAB_X4_Y4; Fanout = 2; COMB Node = 'add~374'" {  } { { "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/db/vgatest_cmp.qrpt" "" { Report "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/db/vgatest_cmp.qrpt" Compiler "vgatest" "UNKNOWN" "V1" "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/db/vgatest.quartus_db" { Floorplan "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/" "" "0.123 ns" { add~414 add~374 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.123 ns) 7.508 ns add~419 7 COMB LAB_X4_Y4 2 " "Info: 7: + IC(0.000 ns) + CELL(0.123 ns) = 7.508 ns; Loc. = LAB_X4_Y4; Fanout = 2; COMB Node = 'add~419'" {  } { { "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/db/vgatest_cmp.qrpt" "" { Report "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/db/vgatest_cmp.qrpt" Compiler "vgatest" "UNKNOWN" "V1" "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/db/vgatest.quartus_db" { Floorplan "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/" "" "0.123 ns" { add~374 add~419 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.123 ns) 7.631 ns add~379 8 COMB LAB_X4_Y4 2 " "Info: 8: + IC(0.000 ns) + CELL(0.123 ns) = 7.631 ns; Loc. = LAB_X4_Y4; Fanout = 2; COMB Node = 'add~379'" {  } { { "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/db/vgatest_cmp.qrpt" "" { Report "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/db/vgatest_cmp.qrpt" Compiler "vgatest" "UNKNOWN" "V1" "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/db/vgatest.quartus_db" { Floorplan "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/" "" "0.123 ns" { add~419 add~379 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.399 ns) 8.030 ns add~384 9 COMB LAB_X4_Y4 5 " "Info: 9: + IC(0.000 ns) + CELL(0.399 ns) = 8.030 ns; Loc. = LAB_X4_Y4; Fanout = 5; COMB Node = 'add~384'" {  } { { "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/db/vgatest_cmp.qrpt" "" { Report "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/db/vgatest_cmp.qrpt" Compiler "vgatest" "UNKNOWN" "V1" "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/db/vgatest.quartus_db" { Floorplan "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/" "" "0.399 ns" { add~379 add~384 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.234 ns) 9.264 ns add~397 10 COMB LAB_X4_Y4 1 " "Info: 10: + IC(0.000 ns) + CELL(1.234 ns) = 9.264 ns; Loc. = LAB_X4_Y4; Fanout = 1; COMB Node = 'add~397'" {  } { { "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/db/vgatest_cmp.qrpt" "" { Report "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/db/vgatest_cmp.qrpt" Compiler "vgatest" "UNKNOWN" "V1" "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/db/vgatest.quartus_db" { Floorplan "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/" "" "1.234 ns" { add~384 add~397 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.724 ns) + CELL(1.183 ns) 11.171 ns line_count\[6\] 11 REG LAB_X5_Y4 5 " "Info: 11: + IC(0.724 ns) + CELL(1.183 ns) = 11.171 ns; Loc. = LAB_X5_Y4; Fanout = 5; REG Node = 'line_count\[6\]'" {  } { { "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/db/vgatest_cmp.qrpt" "" { Report "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/db/vgatest_cmp.qrpt" Compiler "vgatest" "UNKNOWN" "V1" "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/db/vgatest.quartus_db" { Floorplan "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/" "" "1.907 ns" { add~397 line_count[6] } "NODE_NAME" } "" } } { "SVGA_TIMING_GENERATION.v" "" { Text "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/SVGA_TIMING_GENERATION.v" 55 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.502 ns 58.20 % " "Info: Total cell delay = 6.502 ns ( 58.20 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.669 ns 41.80 % " "Info: Total interconnect delay = 4.669 ns ( 41.80 % )" {  } {  } 0}  } { { "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/db/vgatest_cmp.qrpt" "" { Report "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/db/vgatest_cmp.qrpt" Compiler "vgatest" "UNKNOWN" "V1" "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/db/vgatest.quartus_db" { Floorplan "H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/" "" "11.171 ns" { pixel_count[9] pixel_count[0]~434 pixel_count[0]~435 reduce_nor~2840 add~414 add~374 add~419 add~379 add~384 add~397 line_count[6] } "NODE_NAME" } "" } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_NOT_USED" "" "Info: Fitter performed an Auto Fit compilation.  No optimizations were skipped because the design's timing and/or routability requirements required full optimization" {  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 0 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Jun 01 13:41:49 2007 " "Info: Processing ended: Fri Jun 01 13:41:49 2007" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0}  } {  } 0}