vgatest.hier_info

来自「利用VHDL实现CPLD（EPM240T100C5）的VGA屏幕输出」· HIER_INFO 代码 · 共 36 行

|vgatest
pixel_clock50 => pixel_clock.CLK
reset => pixel_count[9].ACLR
reset => pixel_count[8].ACLR
reset => pixel_count[7].ACLR
reset => pixel_count[6].ACLR
reset => pixel_count[5].ACLR
reset => pixel_count[4].ACLR
reset => pixel_count[3].ACLR
reset => pixel_count[2].ACLR
reset => pixel_count[1].ACLR
reset => pixel_count[0].ACLR
reset => h_synch~reg0.ACLR
reset => line_count[9].ACLR
reset => line_count[8].ACLR
reset => line_count[7].ACLR
reset => line_count[6].ACLR
reset => line_count[5].ACLR
reset => line_count[4].ACLR
reset => line_count[3].ACLR
reset => line_count[2].ACLR
reset => line_count[1].ACLR
reset => line_count[0].ACLR
reset => v_synch~reg0.ACLR
reset => pixel_count[10].ACLR
h_synch <= h_synch~reg0.DB_MAX_OUTPUT_PORT_TYPE
v_synch <= v_synch~reg0.DB_MAX_OUTPUT_PORT_TYPE
R[0] <= R[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
R[1] <= R[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
G[0] <= G[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
G[1] <= G[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
B[0] <= B[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
B[1] <= B[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE