vgatest.map.rpt

利用VHDL实现CPLD（EPM240T100C5）的VGA屏幕输出

+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                                      ;
+----------------------------------+-----------------+------------------------+-------------------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type              ; File Name with Absolute Path                                                  ;
+----------------------------------+-----------------+------------------------+-------------------------------------------------------------------------------+
; svga_defines.v                   ; yes             ; User Verilog HDL File  ; H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/svga_defines.v           ;
; SVGA_TIMING_GENERATION.v         ; yes             ; User Verilog HDL File  ; H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/SVGA_TIMING_GENERATION.v ;
+----------------------------------+-----------------+------------------------+-------------------------------------------------------------------------------+


+-------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary     ;
+-----------------------------------+-------------+
; Resource                          ; Usage       ;
+-----------------------------------+-------------+
; Total logic elements              ; 102         ;
; Total combinational functions     ; 86          ;
;     -- Total 4-input functions    ; 53          ;
;     -- Total 3-input functions    ; 7           ;
;     -- Total 2-input functions    ; 6           ;
;     -- Total 1-input functions    ; 20          ;
;     -- Total 0-input functions    ; 0           ;
; Combinational cells for routing   ; 0           ;
; Total registers                   ; 30          ;
; Total logic cells in carry chains ; 21          ;
; I/O pins                          ; 10          ;
; Maximum fan-out node              ; pixel_clock ;
; Maximum fan-out                   ; 30          ;
; Total fan-out                     ; 361         ;
; Average fan-out                   ; 3.22        ;
+-----------------------------------+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                      ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+
; |vgatest                   ; 102 (102)   ; 30           ; 0          ; 10   ; 0            ; 72 (72)      ; 16 (16)           ; 14 (14)          ; 21 (21)         ; |vgatest            ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 30    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 23    ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in H:/work/docs/dboard/epm240/ver1/firmware/VGA_test50m/vgatest.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version
    Info: Processing started: Fri Jun 01 13:41:41 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off vgatest -c vgatest
Info: Found 0 design units, including 0 entities, in source file svga_defines.v
Info: Found 1 design units, including 1 entities, in source file SVGA_TIMING_GENERATION.v
    Info: Found entity 1: vgatest
Info: Elaborating entity "vgatest" for the top level hierarchy
Warning: Verilog HDL assignment warning at SVGA_TIMING_GENERATION.v(79): truncated value with size 32 to match size of target (11)
Warning: Verilog HDL assignment warning at SVGA_TIMING_GENERATION.v(116): truncated value with size 32 to match size of target (10)
Warning: (10271) Verilog HDL Case Statement warning at SVGA_TIMING_GENERATION.v(142): size of case item expression (32) exceeds the size of the case expression (11)
Warning: (10271) Verilog HDL Case Statement warning at SVGA_TIMING_GENERATION.v(148): size of case item expression (32) exceeds the size of the case expression (11)
Warning: (10271) Verilog HDL Case Statement warning at SVGA_TIMING_GENERATION.v(154): size of case item expression (32) exceeds the size of the case expression (11)
Warning: (10271) Verilog HDL Case Statement warning at SVGA_TIMING_GENERATION.v(160): size of case item expression (32) exceeds the size of the case expression (11)
Warning: (10271) Verilog HDL Case Statement warning at SVGA_TIMING_GENERATION.v(166): size of case item expression (32) exceeds the size of the case expression (11)
Warning: (10271) Verilog HDL Case Statement warning at SVGA_TIMING_GENERATION.v(172): size of case item expression (32) exceeds the size of the case expression (11)
Warning: (10271) Verilog HDL Case Statement warning at SVGA_TIMING_GENERATION.v(178): size of case item expression (32) exceeds the size of the case expression (11)
Warning: (10271) Verilog HDL Case Statement warning at SVGA_TIMING_GENERATION.v(184): size of case item expression (32) exceeds the size of the case expression (11)
Warning: (10271) Verilog HDL Case Statement warning at SVGA_TIMING_GENERATION.v(190): size of case item expression (32) exceeds the size of the case expression (11)
Warning: (10271) Verilog HDL Case Statement warning at SVGA_TIMING_GENERATION.v(196): size of case item expression (32) exceeds the size of the case expression (11)
Warning: (10271) Verilog HDL Case Statement warning at SVGA_TIMING_GENERATION.v(202): size of case item expression (32) exceeds the size of the case expression (11)
Warning: (10271) Verilog HDL Case Statement warning at SVGA_TIMING_GENERATION.v(208): size of case item expression (32) exceeds the size of the case expression (11)
Warning: (10271) Verilog HDL Case Statement warning at SVGA_TIMING_GENERATION.v(214): size of case item expression (32) exceeds the size of the case expression (11)
Warning: (10271) Verilog HDL Case Statement warning at SVGA_TIMING_GENERATION.v(220): size of case item expression (32) exceeds the size of the case expression (11)
Warning: (10271) Verilog HDL Case Statement warning at SVGA_TIMING_GENERATION.v(226): size of case item expression (32) exceeds the size of the case expression (11)
Warning: (10271) Verilog HDL Case Statement warning at SVGA_TIMING_GENERATION.v(232): size of case item expression (32) exceeds the size of the case expression (11)
Info: Implemented 112 device resources after synthesis - the final resource count might be different
    Info: Implemented 2 input pins
    Info: Implemented 8 output pins
    Info: Implemented 102 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 18 warnings
    Info: Processing ended: Fri Jun 01 13:41:44 2007
    Info: Elapsed time: 00:00:04