vgatest.map.summary

来自「利用VHDL实现CPLD（EPM240T100C5）的VGA屏幕输出」· SUMMARY 代码 · 共 13 行

Flow Status : Successful - Fri Jun 01 13:41:44 2007
Quartus II Version : 5.0 Build 168 06/22/2005 SP 1 SJ Full Version
Revision Name : vgatest
Top-level Entity Name : vgatest
Family : MAX II
Device : EPM240T100C5
Timing Models : Final
Met timing requirements : N/A
Total logic elements : 102
Total pins : 10
Total virtual pins : 0
UFM blocks : 0