vgatest.tan.rpt

利用VHDL实现CPLD（EPM240T100C5）的VGA屏幕输出

; N/A   ; None         ; 12.096 ns  ; R[0]~reg0    ; R[0]    ; pixel_clock50 ;
; N/A   ; None         ; 12.062 ns  ; G[0]~reg0    ; G[0]    ; pixel_clock50 ;
; N/A   ; None         ; 12.043 ns  ; B[1]~reg0    ; B[1]    ; pixel_clock50 ;
; N/A   ; None         ; 11.946 ns  ; R[1]~reg0    ; R[1]    ; pixel_clock50 ;
; N/A   ; None         ; 11.931 ns  ; v_synch~reg0 ; v_synch ; pixel_clock50 ;
; N/A   ; None         ; 11.446 ns  ; G[1]~reg0    ; G[1]    ; pixel_clock50 ;
; N/A   ; None         ; 10.797 ns  ; h_synch~reg0 ; h_synch ; pixel_clock50 ;
; N/A   ; None         ; 10.763 ns  ; B[0]~reg0    ; B[0]    ; pixel_clock50 ;
+-------+--------------+------------+--------------+---------+---------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version
    Info: Processing started: Fri Jun 01 13:41:52 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off vgatest -c vgatest
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "pixel_clock50" is an undefined clock
Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "pixel_clock" as buffer
Info: Clock "pixel_clock50" has Internal fmax of 92.77 MHz between source register "pixel_count[1]" and destination register "R[1]~reg0" (period= 10.779 ns)
    Info: + Longest register to register delay is 10.070 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X3_Y4_N6; Fanout = 6; REG Node = 'pixel_count[1]'
        Info: 2: + IC(1.361 ns) + CELL(0.914 ns) = 2.275 ns; Loc. = LC_X2_Y4_N2; Fanout = 3; COMB Node = 'reduce_nor~2844'
        Info: 3: + IC(0.772 ns) + CELL(0.200 ns) = 3.247 ns; Loc. = LC_X2_Y4_N8; Fanout = 3; COMB Node = 'reduce_nor~2845'
        Info: 4: + IC(0.305 ns) + CELL(0.200 ns) = 3.752 ns; Loc. = LC_X2_Y4_N9; Fanout = 2; COMB Node = 'reduce_nor~2846'
        Info: 5: + IC(2.471 ns) + CELL(0.200 ns) = 6.423 ns; Loc. = LC_X7_Y4_N1; Fanout = 3; COMB Node = 'reduce_nor~19'
        Info: 6: + IC(0.729 ns) + CELL(0.200 ns) = 7.352 ns; Loc. = LC_X7_Y4_N0; Fanout = 1; COMB Node = 'Select~562'
        Info: 7: + IC(1.914 ns) + CELL(0.804 ns) = 10.070 ns; Loc. = LC_X7_Y3_N5; Fanout = 2; REG Node = 'R[1]~reg0'
        Info: Total cell delay = 2.518 ns ( 25.00 % )
        Info: Total interconnect delay = 7.552 ns ( 75.00 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "pixel_clock50" to destination register is 7.298 ns
            Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 1; CLK Node = 'pixel_clock50'
            Info: 2: + IC(1.177 ns) + CELL(1.294 ns) = 3.634 ns; Loc. = LC_X2_Y3_N4; Fanout = 30; REG Node = 'pixel_clock'
            Info: 3: + IC(2.746 ns) + CELL(0.918 ns) = 7.298 ns; Loc. = LC_X7_Y3_N5; Fanout = 2; REG Node = 'R[1]~reg0'
            Info: Total cell delay = 3.375 ns ( 46.25 % )
            Info: Total interconnect delay = 3.923 ns ( 53.75 % )
        Info: - Longest clock path from clock "pixel_clock50" to source register is 7.298 ns
            Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 1; CLK Node = 'pixel_clock50'
            Info: 2: + IC(1.177 ns) + CELL(1.294 ns) = 3.634 ns; Loc. = LC_X2_Y3_N4; Fanout = 30; REG Node = 'pixel_clock'
            Info: 3: + IC(2.746 ns) + CELL(0.918 ns) = 7.298 ns; Loc. = LC_X3_Y4_N6; Fanout = 6; REG Node = 'pixel_count[1]'
            Info: Total cell delay = 3.375 ns ( 46.25 % )
            Info: Total interconnect delay = 3.923 ns ( 53.75 % )
    Info: + Micro clock to output delay of source is 0.376 ns
    Info: + Micro setup delay of destination is 0.333 ns
Info: tco from clock "pixel_clock50" to destination pin "R[0]" through register "R[0]~reg0" is 12.096 ns
    Info: + Longest clock path from clock "pixel_clock50" to source register is 7.298 ns
        Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 1; CLK Node = 'pixel_clock50'
        Info: 2: + IC(1.177 ns) + CELL(1.294 ns) = 3.634 ns; Loc. = LC_X2_Y3_N4; Fanout = 30; REG Node = 'pixel_clock'
        Info: 3: + IC(2.746 ns) + CELL(0.918 ns) = 7.298 ns; Loc. = LC_X7_Y3_N3; Fanout = 2; REG Node = 'R[0]~reg0'
        Info: Total cell delay = 3.375 ns ( 46.25 % )
        Info: Total interconnect delay = 3.923 ns ( 53.75 % )
    Info: + Micro clock to output delay of source is 0.376 ns
    Info: + Longest register to pin delay is 4.422 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X7_Y3_N3; Fanout = 2; REG Node = 'R[0]~reg0'
        Info: 2: + IC(2.100 ns) + CELL(2.322 ns) = 4.422 ns; Loc. = PIN_71; Fanout = 0; PIN Node = 'R[0]'
        Info: Total cell delay = 2.322 ns ( 52.51 % )
        Info: Total interconnect delay = 2.100 ns ( 47.49 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings
    Info: Processing ended: Fri Jun 01 13:41:53 2007
    Info: Elapsed time: 00:00:02