vgatest.fit.summary

利用VHDL实现CPLD（EPM240T100C5）的VGA屏幕输出

Flow Status : Successful - Fri Jun 01 13:41:49 2007
Quartus II Version : 5.0 Build 168 06/22/2005 SP 1 SJ Full Version
Revision Name : vgatest
Top-level Entity Name : vgatest
Family : MAX II
Device : EPM240T100C5
Timing Models : Final
Met timing requirements : N/A
Total logic elements : 89 / 240 ( 37 % )
Total pins : 10 / 80 ( 12 % )
Total virtual pins : 0
UFM blocks : 0 / 1 ( 0 % )