time.v.bak

ALTERA上DE2平台

module Time
(
KEY,SW,CLOCK_50,
LEDG,HEX7,HEX6,HEX3,HEX2,HEX1,HEX0
);
input [3:0] KEY;
input [17:0] SW;
input CLOCK_50;
output [8:0] LEDG;
output [6:0] HEX7,HEX6,HEX3,HEX2,HEX1,HEX0;
wire SecClk;
wire [7:0] Second,Minute,Hour;


SecClkGen SCG1(CLOCK_50,SW[17],KEY[1],Second,SecClk);
DecDis SC1(Second[7:4],SecClk,SW[17],HEX1);
DecDis SC0(Second[3:0],SecClk,SW[17],HEX0);

MinClkGen MCG1(CLOCK_50,SW[17],KEY[2],Minute);
DecDis MC1(Minute[7:4],SecClk,SW[17],HEX3);
DecDis MC0(Minute[3:0],SecClk,SW[17],HEX2);

HouClkGen HCG1(CLOCK_50,SW[17],KEY[3],Hour);
DecDis HC1(Hour[7:4],SecClk,SW[17],HEX7);
DecDis HC0(Hour[3:0],SecClk,SW[17],HEX6);

endmodule

module DecDis (DecVal,clc,rst,HexVal);
input [3:0] DecVal;
input clc;
input rst;
output reg [6:0] HexVal;
always @(posedge clc or posedge rst)
begin
	if (rst)
		HexVal = 7'b1111111;
	else
	case (DecVal)
		4'h0:	HexVal = 7'b 1000000;
		4'h1:	HexVal = 7'b 1111001;
		4'h2:	HexVal = 7'b 0100100;
		4'h3:	HexVal = 7'b 0110000;
		4'h4:	HexVal = 7'b 0011001;
		4'h5:	HexVal = 7'b 0010010;
		4'h6:	HexVal = 7'b 0000010;
		4'h7:	HexVal = 7'b 1111000;
		4'h8:	HexVal = 7'b 0000000;
		4'h9:	HexVal = 7'b 0010000;
		4'ha:	HexVal = 7'b 0001000;
		4'hb:	HexVal = 7'b 0000011;
		4'hc:	HexVal = 7'b 1000110;
		4'hd:	HexVal = 7'b 0100001;
		4'he:	HexVal = 7'b 0000110;
		4'hf:	HexVal = 7'b 0001110;
	endcase
end
endmodule

module SecClkGen(clk,rst,plus,Second,SecClk);
input clk,rst,plus;
output [7:0] Second;
output SecClk;
reg [25:0] countc;
reg [5:0] counts;

always @ (posedge clk or posedge rst)
begin
    if (rst)
		countc <= 26'h0;
	else
		if (countc == 26'h31FFFFF) // 11_0001_0..0 = 50M-1
		begin
			countc <= 26'h0;
			if (counts == 6'h3b) // 11_1011 = 60-1
				counts <= 6'h0;
			else
				counts <= counts + 6'h1;
		end
		else
			countc <= countc + 26'h1;
end
assign Second[7:4] = counts / 4'b1010;
assign Second[3:0] = counts % 4'b1010;
assign SecClk = countc[24];
endmodule

module MinClkGen(clk,rst,plus,Minute);
input clk,rst,plus;
output [7:0] Minute;
reg [31:0] countc;
reg [5:0] countm;

always @ (posedge clk or posedge rst)
begin
    if (rst)
		countc <= 32'h0;
	else
		if (countc == 32'hBB7FFFFF) 
		begin
			countc <= 32'h0;
			if (countm == 6'h3b) // 11_1011 = 60-1
				countm <= 6'h0;
			else
				countm <= countm + 6'h1;
		end
		else
			countc <= countc + 32'h1;
end
assign Minute[7:4] = countm / 4'b1010;
assign Minute[3:0] = countm % 4'b1010;
endmodule

module HouClkGen(clk,rst,plus,Hour);
input clk,rst,plus;
output [7:0] Hour;
reg [43:0] countc;
reg [4:0] counth;

always @ (posedge clk or posedge rst)
begin
    if (rst)
		countc <= 44'h0;
	else
		if (countc == 44'h41EAFFFFFFF) 
		begin
			countc <= 44'h0;
			if (counth == 5'h17) // 1_0111 = 24-1
				counth <= 5'h0;
			else
				counth <= counth + 5'h1;
		end
		else
			countc <= countc + 44'h1;
end


assign Hour[7:4] = counth / 4'b1010;
assign Hour[3:0] = counth % 4'b1010;
endmodule