time.map.qmsg

ALTERA上DE2平台

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Elaboration Quartus II " "Info: Running Quartus II Analysis & Elaboration" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 207 03/18/2008 Service Pack 3 SJ Full Version " "Info: Version 7.2 Build 207 03/18/2008 Service Pack 3 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Jul 14 19:37:17 2008 " "Info: Processing started: Mon Jul 14 19:37:17 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off Time -c Time --analysis_and_elaboration " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off Time -c Time --analysis_and_elaboration" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Time.v 5 5 " "Info: Found 5 design units, including 5 entities, in source file Time.v" { { "Info" "ISGN_ENTITY_NAME" "1 Time " "Info: Found entity 1: Time" {  } { { "Time.v" "" { Text "D:/PROGRAMING/fpga/Time/Time.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "2 DecDis " "Info: Found entity 2: DecDis" {  } { { "Time.v" "" { Text "D:/PROGRAMING/fpga/Time/Time.v" 29 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "3 SecClkGen " "Info: Found entity 3: SecClkGen" {  } { { "Time.v" "" { Text "D:/PROGRAMING/fpga/Time/Time.v" 60 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "4 MinClkGen " "Info: Found entity 4: MinClkGen" {  } { { "Time.v" "" { Text "D:/PROGRAMING/fpga/Time/Time.v" 88 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "5 HouClkGen " "Info: Found entity 5: HouClkGen" {  } { { "Time.v" "" { Text "D:/PROGRAMING/fpga/Time/Time.v" 114 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "Time " "Info: Elaborating entity \"Time\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "LEDG\[8\] Time.v(9) " "Warning (10034): Output port \"LEDG\[8\]\" at Time.v(9) has no driver" {  } { { "Time.v" "" { Text "D:/PROGRAMING/fpga/Time/Time.v" 9 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "LEDG\[7\] Time.v(9) " "Warning (10034): Output port \"LEDG\[7\]\" at Time.v(9) has no driver" {  } { { "Time.v" "" { Text "D:/PROGRAMING/fpga/Time/Time.v" 9 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "LEDG\[6\] Time.v(9) " "Warning (10034): Output port \"LEDG\[6\]\" at Time.v(9) has no driver" {  } { { "Time.v" "" { Text "D:/PROGRAMING/fpga/Time/Time.v" 9 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "LEDG\[5\] Time.v(9) " "Warning (10034): Output port \"LEDG\[5\]\" at Time.v(9) has no driver" {  } { { "Time.v" "" { Text "D:/PROGRAMING/fpga/Time/Time.v" 9 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "LEDG\[4\] Time.v(9) " "Warning (10034): Output port \"LEDG\[4\]\" at Time.v(9) has no driver" {  } { { "Time.v" "" { Text "D:/PROGRAMING/fpga/Time/Time.v" 9 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "LEDG\[3\] Time.v(9) " "Warning (10034): Output port \"LEDG\[3\]\" at Time.v(9) has no driver" {  } { { "Time.v" "" { Text "D:/PROGRAMING/fpga/Time/Time.v" 9 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "LEDG\[2\] Time.v(9) " "Warning (10034): Output port \"LEDG\[2\]\" at Time.v(9) has no driver" {  } { { "Time.v" "" { Text "D:/PROGRAMING/fpga/Time/Time.v" 9 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "LEDG\[1\] Time.v(9) " "Warning (10034): Output port \"LEDG\[1\]\" at Time.v(9) has no driver" {  } { { "Time.v" "" { Text "D:/PROGRAMING/fpga/Time/Time.v" 9 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "LEDG\[0\] Time.v(9) " "Warning (10034): Output port \"LEDG\[0\]\" at Time.v(9) has no driver" {  } { { "Time.v" "" { Text "D:/PROGRAMING/fpga/Time/Time.v" 9 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "SecClkGen SecClkGen:SCG1 " "Info: Elaborating entity \"SecClkGen\" for hierarchy \"SecClkGen:SCG1\"" {  } { { "Time.v" "SCG1" { Text "D:/PROGRAMING/fpga/Time/Time.v" 15 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "6 4 Time.v(83) " "Warning (10230): Verilog HDL assignment warning at Time.v(83): truncated value with size 6 to match size of target (4)" {  } { { "Time.v" "" { Text "D:/PROGRAMING/fpga/Time/Time.v" 83 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "6 4 Time.v(84) " "Warning (10230): Verilog HDL assignment warning at Time.v(84): truncated value with size 6 to match size of target (4)" {  } { { "Time.v" "" { Text "D:/PROGRAMING/fpga/Time/Time.v" 84 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "DecDis DecDis:SC1 " "Info: Elaborating entity \"DecDis\" for hierarchy \"DecDis:SC1\"" {  } { { "Time.v" "SC1" { Text "D:/PROGRAMING/fpga/Time/Time.v" 16 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "MinClkGen MinClkGen:MCG1 " "Info: Elaborating entity \"MinClkGen\" for hierarchy \"MinClkGen:MCG1\"" {  } { { "Time.v" "MCG1" { Text "D:/PROGRAMING/fpga/Time/Time.v" 19 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "6 4 Time.v(110) " "Warning (10230): Verilog HDL assignment warning at Time.v(110): truncated value with size 6 to match size of target (4)" {  } { { "Time.v" "" { Text "D:/PROGRAMING/fpga/Time/Time.v" 110 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "6 4 Time.v(111) " "Warning (10230): Verilog HDL assignment warning at Time.v(111): truncated value with size 6 to match size of target (4)" {  } { { "Time.v" "" { Text "D:/PROGRAMING/fpga/Time/Time.v" 111 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "HouClkGen HouClkGen:HCG1 " "Info: Elaborating entity \"HouClkGen\" for hierarchy \"HouClkGen:HCG1\"" {  } { { "Time.v" "HCG1" { Text "D:/PROGRAMING/fpga/Time/Time.v" 23 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "5 4 Time.v(138) " "Warning (10230): Verilog HDL assignment warning at Time.v(138): truncated value with size 5 to match size of target (4)" {  } { { "Time.v" "" { Text "D:/PROGRAMING/fpga/Time/Time.v" 138 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "5 4 Time.v(139) " "Warning (10230): Verilog HDL assignment warning at Time.v(139): truncated value with size 5 to match size of target (4)" {  } { { "Time.v" "" { Text "D:/PROGRAMING/fpga/Time/Time.v" 139 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Elaboration 0 s 15 s Quartus II " "Info: Quartus II Analysis & Elaboration was successful. 0 errors, 15 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "137 " "Info: Allocated 137 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Mon Jul 14 19:37:19 2008 " "Info: Processing ended: Mon Jul 14 19:37:19 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}