prev_cmp_time.tan.qmsg

ALTERA上DE2平台

{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "CLOCK_50 168 " "Warning: Circuit may not operate. Detected 168 non-operational path(s) clocked by clock \"CLOCK_50\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0 "" 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "SecClkGen:SCG1\|counts\[0\] DecDis:SC0\|HexVal\[2\] CLOCK_50 3.176 ns " "Info: Found hold time violation between source  pin or register \"SecClkGen:SCG1\|counts\[0\]\" and destination pin or register \"DecDis:SC0\|HexVal\[2\]\" for clock \"CLOCK_50\" (Hold time is 3.176 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "3.872 ns + Largest " "Info: + Largest clock skew is 3.872 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK_50 destination 6.546 ns + Longest register " "Info: + Longest clock path from clock \"CLOCK_50\" to destination register is 6.546 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns CLOCK_50 1 CLK PIN_N2 2 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 2; CLK Node = 'CLOCK_50'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "Time.v" "" { Text "D:/PROGRAMING/fpga/Time/Time.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.245 ns) + CELL(0.787 ns) 3.031 ns SecClkGen:SCG1\|countc\[24\] 2 REG LCFF_X30_Y18_N31 5 " "Info: 2: + IC(1.245 ns) + CELL(0.787 ns) = 3.031 ns; Loc. = LCFF_X30_Y18_N31; Fanout = 5; REG Node = 'SecClkGen:SCG1\|countc\[24\]'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.032 ns" { CLOCK_50 SecClkGen:SCG1|countc[24] } "NODE_NAME" } } { "Time.v" "" { Text "D:/PROGRAMING/fpga/Time/Time.v" 74 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.971 ns) + CELL(0.000 ns) 5.002 ns SecClkGen:SCG1\|countc\[24\]~clkctrl 3 COMB CLKCTRL_G13 41 " "Info: 3: + IC(1.971 ns) + CELL(0.000 ns) = 5.002 ns; Loc. = CLKCTRL_G13; Fanout = 41; COMB Node = 'SecClkGen:SCG1\|countc\[24\]~clkctrl'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.971 ns" { SecClkGen:SCG1|countc[24] SecClkGen:SCG1|countc[24]~clkctrl } "NODE_NAME" } } { "Time.v" "" { Text "D:/PROGRAMING/fpga/Time/Time.v" 74 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.007 ns) + CELL(0.537 ns) 6.546 ns DecDis:SC0\|HexVal\[2\] 4 REG LCFF_X54_Y7_N1 1 " "Info: 4: + IC(1.007 ns) + CELL(0.537 ns) = 6.546 ns; Loc. = LCFF_X54_Y7_N1; Fanout = 1; REG Node = 'DecDis:SC0\|HexVal\[2\]'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.544 ns" { SecClkGen:SCG1|countc[24]~clkctrl DecDis:SC0|HexVal[2] } "NODE_NAME" } } { "Time.v" "" { Text "D:/PROGRAMING/fpga/Time/Time.v" 41 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.323 ns ( 35.49 % ) " "Info: Total cell delay = 2.323 ns ( 35.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.223 ns ( 64.51 % ) " "Info: Total interconnect delay = 4.223 ns ( 64.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.546 ns" { CLOCK_50 SecClkGen:SCG1|countc[24] SecClkGen:SCG1|countc[24]~clkctrl DecDis:SC0|HexVal[2] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.546 ns" { CLOCK_50 {} CLOCK_50~combout {} SecClkGen:SCG1|countc[24] {} SecClkGen:SCG1|countc[24]~clkctrl {} DecDis:SC0|HexVal[2] {} } { 0.000ns 0.000ns 1.245ns 1.971ns 1.007ns } { 0.000ns 0.999ns 0.787ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK_50 source 2.674 ns - Shortest register " "Info: - Shortest clock path from clock \"CLOCK_50\" to source register is 2.674 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns CLOCK_50 1 CLK PIN_N2 2 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 2; CLK Node = 'CLOCK_50'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "Time.v" "" { Text "D:/PROGRAMING/fpga/Time/Time.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns CLOCK_50~clkctrl 2 COMB CLKCTRL_G2 74 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 74; COMB Node = 'CLOCK_50~clkctrl'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.118 ns" { CLOCK_50 CLOCK_50~clkctrl } "NODE_NAME" } } { "Time.v" "" { Text "D:/PROGRAMING/fpga/Time/Time.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.020 ns) + CELL(0.537 ns) 2.674 ns SecClkGen:SCG1\|counts\[0\] 3 REG LCFF_X54_Y7_N5 11 " "Info: 3: + IC(1.020 ns) + CELL(0.537 ns) = 2.674 ns; Loc. = LCFF_X54_Y7_N5; Fanout = 11; REG Node = 'SecClkGen:SCG1\|counts\[0\]'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.557 ns" { CLOCK_50~clkctrl SecClkGen:SCG1|counts[0] } "NODE_NAME" } } { "Time.v" "" { Text "D:/PROGRAMING/fpga/Time/Time.v" 74 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.44 % ) " "Info: Total cell delay = 1.536 ns ( 57.44 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.138 ns ( 42.56 % ) " "Info: Total interconnect delay = 1.138 ns ( 42.56 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.674 ns" { CLOCK_50 CLOCK_50~clkctrl SecClkGen:SCG1|counts[0] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.674 ns" { CLOCK_50 {} CLOCK_50~combout {} CLOCK_50~clkctrl {} SecClkGen:SCG1|counts[0] {} } { 0.000ns 0.000ns 0.118ns 1.020ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.546 ns" { CLOCK_50 SecClkGen:SCG1|countc[24] SecClkGen:SCG1|countc[24]~clkctrl DecDis:SC0|HexVal[2] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.546 ns" { CLOCK_50 {} CLOCK_50~combout {} SecClkGen:SCG1|countc[24] {} SecClkGen:SCG1|countc[24]~clkctrl {} DecDis:SC0|HexVal[2] {} } { 0.000ns 0.000ns 1.245ns 1.971ns 1.007ns } { 0.000ns 0.999ns 0.787ns 0.000ns 0.537ns } "" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.674 ns" { CLOCK_50 CLOCK_50~clkctrl SecClkGen:SCG1|counts[0] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.674 ns" { CLOCK_50 {} CLOCK_50~combout {} CLOCK_50~clkctrl {} SecClkGen:SCG1|counts[0] {} } { 0.000ns 0.000ns 0.118ns 1.020ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns - " "Info: - Micro clock to output delay of source is 0.250 ns" {  } { { "Time.v" "" { Text "D:/PROGRAMING/fpga/Time/Time.v" 74 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.712 ns - Shortest register register " "Info: - Shortest register to register delay is 0.712 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns SecClkGen:SCG1\|counts\[0\] 1 REG LCFF_X54_Y7_N5 11 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X54_Y7_N5; Fanout = 11; REG Node = 'SecClkGen:SCG1\|counts\[0\]'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { SecClkGen:SCG1|counts[0] } "NODE_NAME" } } { "Time.v" "" { Text "D:/PROGRAMING/fpga/Time/Time.v" 74 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.353 ns) + CELL(0.275 ns) 0.628 ns DecDis:SC0\|WideOr4~15 2 COMB LCCOMB_X54_Y7_N0 1 " "Info: 2: + IC(0.353 ns) + CELL(0.275 ns) = 0.628 ns; Loc. = LCCOMB_X54_Y7_N0; Fanout = 1; COMB Node = 'DecDis:SC0\|WideOr4~15'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.628 ns" { SecClkGen:SCG1|counts[0] DecDis:SC0|WideOr4~15 } "NODE_NAME" } } { "Time.v" "" { Text "D:/PROGRAMING/fpga/Time/Time.v" 41 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 0.712 ns DecDis:SC0\|HexVal\[2\] 3 REG LCFF_X54_Y7_N1 1 " "Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 0.712 ns; Loc. = LCFF_X54_Y7_N1; Fanout = 1; REG Node = 'DecDis:SC0\|HexVal\[2\]'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.084 ns" { DecDis:SC0|WideOr4~15 DecDis:SC0|HexVal[2] } "NODE_NAME" } } { "Time.v" "" { Text "D:/PROGRAMING/fpga/Time/Time.v" 41 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.359 ns ( 50.42 % ) " "Info: Total cell delay = 0.359 ns ( 50.42 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.353 ns ( 49.58 % ) " "Info: Total interconnect delay = 0.353 ns ( 49.58 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.712 ns" { SecClkGen:SCG1|counts[0] DecDis:SC0|WideOr4~15 DecDis:SC0|HexVal[2] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "0.712 ns" { SecClkGen:SCG1|counts[0] {} DecDis:SC0|WideOr4~15 {} DecDis:SC0|HexVal[2] {} } { 0.000ns 0.353ns 0.000ns } { 0.000ns 0.275ns 0.084ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.266 ns + " "Info: + Micro hold delay of destination is 0.266 ns" {  } { { "Time.v" "" { Text "D:/PROGRAMING/fpga/Time/Time.v" 41 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.546 ns" { CLOCK_50 SecClkGen:SCG1|countc[24] SecClkGen:SCG1|countc[24]~clkctrl DecDis:SC0|HexVal[2] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.546 ns" { CLOCK_50 {} CLOCK_50~combout {} SecClkGen:SCG1|countc[24] {} SecClkGen:SCG1|countc[24]~clkctrl {} DecDis:SC0|HexVal[2] {} } { 0.000ns 0.000ns 1.245ns 1.971ns 1.007ns } { 0.000ns 0.999ns 0.787ns 0.000ns 0.537ns } "" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.674 ns" { CLOCK_50 CLOCK_50~clkctrl SecClkGen:SCG1|counts[0] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.674 ns" { CLOCK_50 {} CLOCK_50~combout {} CLOCK_50~clkctrl {} SecClkGen:SCG1|counts[0] {} } { 0.000ns 0.000ns 0.118ns 1.020ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.712 ns" { SecClkGen:SCG1|counts[0] DecDis:SC0|WideOr4~15 DecDis:SC0|HexVal[2] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "0.712 ns" { SecClkGen:SCG1|counts[0] {} DecDis:SC0|WideOr4~15 {} DecDis:SC0|HexVal[2] {} } { 0.000ns 0.353ns 0.000ns } { 0.000ns 0.275ns 0.084ns } "" } }  } 0 0 "Found hold time violation between source  pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0 "" 0}