prev_cmp_time.tan.qmsg

ALTERA上DE2平台

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "SecClkGen:SCG1\|countc\[24\] " "Info: Detected ripple clock \"SecClkGen:SCG1\|countc\[24\]\" as buffer" {  } { { "Time.v" "" { Text "D:/PROGRAMING/fpga/Time/Time.v" 74 -1 0 } } { "e:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "SecClkGen:SCG1\|countc\[24\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLOCK_50 register MinClkGen:MCG1\|countm\[3\] register DecDis:MC1\|HexVal\[1\] 154.54 MHz 6.471 ns Internal " "Info: Clock \"CLOCK_50\" has Internal fmax of 154.54 MHz between source register \"MinClkGen:MCG1\|countm\[3\]\" and destination register \"DecDis:MC1\|HexVal\[1\]\" (period= 6.471 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.167 ns + Longest register register " "Info: + Longest register to register delay is 10.167 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns MinClkGen:MCG1\|countm\[3\] 1 REG LCFF_X54_Y21_N23 11 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X54_Y21_N23; Fanout = 11; REG Node = 'MinClkGen:MCG1\|countm\[3\]'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { MinClkGen:MCG1|countm[3] } "NODE_NAME" } } { "Time.v" "" { Text "D:/PROGRAMING/fpga/Time/Time.v" 101 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.524 ns) + CELL(0.393 ns) 0.917 ns MinClkGen:MCG1\|lpm_divide:Div0\|lpm_divide_vcm:auto_generated\|sign_div_unsign_9kh:divider\|alt_u_div_kve:divider\|add_sub_3_result_int\[1\]~15 2 COMB LCCOMB_X53_Y21_N10 2 " "Info: 2: + IC(0.524 ns) + CELL(0.393 ns) = 0.917 ns; Loc. = LCCOMB_X53_Y21_N10; Fanout = 2; COMB Node = 'MinClkGen:MCG1\|lpm_divide:Div0\|lpm_divide_vcm:auto_generated\|sign_div_unsign_9kh:divider\|alt_u_div_kve:divider\|add_sub_3_result_int\[1\]~15'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.917 ns" { MinClkGen:MCG1|countm[3] MinClkGen:MCG1|lpm_divide:Div0|lpm_divide_vcm:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|add_sub_3_result_int[1]~15 } "NODE_NAME" } } { "db/alt_u_div_kve.tdf" "" { Text "D:/PROGRAMING/fpga/Time/db/alt_u_div_kve.tdf" 42 22 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 0.988 ns MinClkGen:MCG1\|lpm_divide:Div0\|lpm_divide_vcm:auto_generated\|sign_div_unsign_9kh:divider\|alt_u_div_kve:divider\|add_sub_3_result_int\[2\]~17 3 COMB LCCOMB_X53_Y21_N12 2 " "Info: 3: + IC(0.000 ns) + CELL(0.071 ns) = 0.988 ns; Loc. = LCCOMB_X53_Y21_N12; Fanout = 2; COMB Node = 'MinClkGen:MCG1\|lpm_divide:Div0\|lpm_divide_vcm:auto_generated\|sign_div_unsign_9kh:divider\|alt_u_div_kve:divider\|add_sub_3_result_int\[2\]~17'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { MinClkGen:MCG1|lpm_divide:Div0|lpm_divide_vcm:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|add_sub_3_result_int[1]~15 MinClkGen:MCG1|lpm_divide:Div0|lpm_divide_vcm:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|add_sub_3_result_int[2]~17 } "NODE_NAME" } } { "db/alt_u_div_kve.tdf" "" { Text "D:/PROGRAMING/fpga/Time/db/alt_u_div_kve.tdf" 42 22 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.159 ns) 1.147 ns MinClkGen:MCG1\|lpm_divide:Div0\|lpm_divide_vcm:auto_generated\|sign_div_unsign_9kh:divider\|alt_u_div_kve:divider\|add_sub_3_result_int\[3\]~19 4 COMB LCCOMB_X53_Y21_N14 1 " "Info: 4: + IC(0.000 ns) + CELL(0.159 ns) = 1.147 ns; Loc. = LCCOMB_X53_Y21_N14; Fanout = 1; COMB Node = 'MinClkGen:MCG1\|lpm_divide:Div0\|lpm_divide_vcm:auto_generated\|sign_div_unsign_9kh:divider\|alt_u_div_kve:divider\|add_sub_3_result_int\[3\]~19'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.159 ns" { MinClkGen:MCG1|lpm_divide:Div0|lpm_divide_vcm:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|add_sub_3_result_int[2]~17 MinClkGen:MCG1|lpm_divide:Div0|lpm_divide_vcm:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|add_sub_3_result_int[3]~19 } "NODE_NAME" } } { "db/alt_u_div_kve.tdf" "" { Text "D:/PROGRAMING/fpga/Time/db/alt_u_div_kve.tdf" 42 22 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.410 ns) 1.557 ns MinClkGen:MCG1\|lpm_divide:Div0\|lpm_divide_vcm:auto_generated\|sign_div_unsign_9kh:divider\|alt_u_div_kve:divider\|add_sub_3_result_int\[4\]~20 5 COMB LCCOMB_X53_Y21_N16 17 " "Info: 5: + IC(0.000 ns) + CELL(0.410 ns) = 1.557 ns; Loc. = LCCOMB_X53_Y21_N16; Fanout = 17; COMB Node = 'MinClkGen:MCG1\|lpm_divide:Div0\|lpm_divide_vcm:auto_generated\|sign_div_unsign_9kh:divider\|alt_u_div_kve:divider\|add_sub_3_result_int\[4\]~20'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.410 ns" { MinClkGen:MCG1|lpm_divide:Div0|lpm_divide_vcm:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|add_sub_3_result_int[3]~19 MinClkGen:MCG1|lpm_divide:Div0|lpm_divide_vcm:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|add_sub_3_result_int[4]~20 } "NODE_NAME" } } { "db/alt_u_div_kve.tdf" "" { Text "D:/PROGRAMING/fpga/Time/db/alt_u_div_kve.tdf" 42 22 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.744 ns) + CELL(0.150 ns) 3.451 ns MinClkGen:MCG1\|lpm_divide:Div0\|lpm_divide_vcm:auto_generated\|sign_div_unsign_9kh:divider\|alt_u_div_kve:divider\|StageOut\[18\]~21 6 COMB LCCOMB_X32_Y18_N28 1 " "Info: 6: + IC(1.744 ns) + CELL(0.150 ns) = 3.451 ns; Loc. = LCCOMB_X32_Y18_N28; Fanout = 1; COMB Node = 'MinClkGen:MCG1\|lpm_divide:Div0\|lpm_divide_vcm:auto_generated\|sign_div_unsign_9kh:divider\|alt_u_div_kve:divider\|StageOut\[18\]~21'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.894 ns" { MinClkGen:MCG1|lpm_divide:Div0|lpm_divide_vcm:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|add_sub_3_result_int[4]~20 MinClkGen:MCG1|lpm_divide:Div0|lpm_divide_vcm:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|StageOut[18]~21 } "NODE_NAME" } } { "db/alt_u_div_kve.tdf" "" { Text "D:/PROGRAMING/fpga/Time/db/alt_u_div_kve.tdf" 69 10 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.499 ns) + CELL(0.393 ns) 5.343 ns MinClkGen:MCG1\|lpm_divide:Div0\|lpm_divide_vcm:auto_generated\|sign_div_unsign_9kh:divider\|alt_u_div_kve:divider\|add_sub_4_result_int\[4\]~23 7 COMB LCCOMB_X54_Y22_N24 1 " "Info: 7: + IC(1.499 ns) + CELL(0.393 ns) = 5.343 ns; Loc. = LCCOMB_X54_Y22_N24; Fanout = 1; COMB Node = 'MinClkGen:MCG1\|lpm_divide:Div0\|lpm_divide_vcm:auto_generated\|sign_div_unsign_9kh:divider\|alt_u_div_kve:divider\|add_sub_4_result_int\[4\]~23'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.892 ns" { MinClkGen:MCG1|lpm_divide:Div0|lpm_divide_vcm:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|StageOut[18]~21 MinClkGen:MCG1|lpm_divide:Div0|lpm_divide_vcm:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|add_sub_4_result_int[4]~23 } "NODE_NAME" } } { "db/alt_u_div_kve.tdf" "" { Text "D:/PROGRAMING/fpga/Time/db/alt_u_div_kve.tdf" 47 22 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.410 ns) 5.753 ns MinClkGen:MCG1\|lpm_divide:Div0\|lpm_divide_vcm:auto_generated\|sign_div_unsign_9kh:divider\|alt_u_div_kve:divider\|add_sub_4_result_int\[5\]~24 8 COMB LCCOMB_X54_Y22_N26 15 " "Info: 8: + IC(0.000 ns) + CELL(0.410 ns) = 5.753 ns; Loc. = LCCOMB_X54_Y22_N26; Fanout = 15; COMB Node = 'MinClkGen:MCG1\|lpm_divide:Div0\|lpm_divide_vcm:auto_generated\|sign_div_unsign_9kh:divider\|alt_u_div_kve:divider\|add_sub_4_result_int\[5\]~24'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.410 ns" { MinClkGen:MCG1|lpm_divide:Div0|lpm_divide_vcm:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|add_sub_4_result_int[4]~23 MinClkGen:MCG1|lpm_divide:Div0|lpm_divide_vcm:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|add_sub_4_result_int[5]~24 } "NODE_NAME" } } { "db/alt_u_div_kve.tdf" "" { Text "D:/PROGRAMING/fpga/Time/db/alt_u_div_kve.tdf" 47 22 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.731 ns) + CELL(0.275 ns) 6.759 ns MinClkGen:MCG1\|lpm_divide:Div0\|lpm_divide_vcm:auto_generated\|sign_div_unsign_9kh:divider\|alt_u_div_kve:divider\|StageOut\[22\]~276 9 COMB LCCOMB_X53_Y21_N18 1 " "Info: 9: + IC(0.731 ns) + CELL(0.275 ns) = 6.759 ns; Loc. = LCCOMB_X53_Y21_N18; Fanout = 1; COMB Node = 'MinClkGen:MCG1\|lpm_divide:Div0\|lpm_divide_vcm:auto_generated\|sign_div_unsign_9kh:divider\|alt_u_div_kve:divider\|StageOut\[22\]~276'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.006 ns" { MinClkGen:MCG1|lpm_divide:Div0|lpm_divide_vcm:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|add_sub_4_result_int[5]~24 MinClkGen:MCG1|lpm_divide:Div0|lpm_divide_vcm:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|StageOut[22]~276 } "NODE_NAME" } } { "db/alt_u_div_kve.tdf" "" { Text "D:/PROGRAMING/fpga/Time/db/alt_u_div_kve.tdf" 69 10 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.744 ns) + CELL(0.393 ns) 7.896 ns MinClkGen:MCG1\|lpm_divide:Div0\|lpm_divide_vcm:auto_generated\|sign_div_unsign_9kh:divider\|alt_u_div_kve:divider\|add_sub_5_result_int\[3\]~24 10 COMB LCCOMB_X53_Y18_N20 1 " "Info: 10: + IC(0.744 ns) + CELL(0.393 ns) = 7.896 ns; Loc. = LCCOMB_X53_Y18_N20; Fanout = 1; COMB Node = 'MinClkGen:MCG1\|lpm_divide:Div0\|lpm_divide_vcm:auto_generated\|sign_div_unsign_9kh:divider\|alt_u_div_kve:divider\|add_sub_5_result_int\[3\]~24'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.137 ns" { MinClkGen:MCG1|lpm_divide:Div0|lpm_divide_vcm:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|StageOut[22]~276 MinClkGen:MCG1|lpm_divide:Div0|lpm_divide_vcm:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|add_sub_5_result_int[3]~24 } "NODE_NAME" } } { "db/alt_u_div_kve.tdf" "" { Text "D:/PROGRAMING/fpga/Time/db/alt_u_div_kve.tdf" 52 22 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 7.967 ns MinClkGen:MCG1\|lpm_divide:Div0\|lpm_divide_vcm:auto_generated\|sign_div_unsign_9kh:divider\|alt_u_div_kve:divider\|add_sub_5_result_int\[4\]~26 11 COMB LCCOMB_X53_Y18_N22 1 " "Info: 11: + IC(0.000 ns) + CELL(0.071 ns) = 7.967 ns; Loc. = LCCOMB_X53_Y18_N22; Fanout = 1; COMB Node = 'MinClkGen:MCG1\|lpm_divide:Div0\|lpm_divide_vcm:auto_generated\|sign_div_unsign_9kh:divider\|alt_u_div_kve:divider\|add_sub_5_result_int\[4\]~26'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { MinClkGen:MCG1|lpm_divide:Div0|lpm_divide_vcm:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|add_sub_5_result_int[3]~24 MinClkGen:MCG1|lpm_divide:Div0|lpm_divide_vcm:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|add_sub_5_result_int[4]~26 } "NODE_NAME" } } { "db/alt_u_div_kve.tdf" "" { Text "D:/PROGRAMING/fpga/Time/db/alt_u_div_kve.tdf" 52 22 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.410 ns) 8.377 ns MinClkGen:MCG1\|lpm_divide:Div0\|lpm_divide_vcm:auto_generated\|sign_div_unsign_9kh:divider\|alt_u_div_kve:divider\|add_sub_5_result_int\[5\]~27 12 COMB LCCOMB_X53_Y18_N24 7 " "Info: 12: + IC(0.000 ns) + CELL(0.410 ns) = 8.377 ns; Loc. = LCCOMB_X53_Y18_N24; Fanout = 7; COMB Node = 'MinClkGen:MCG1\|lpm_divide:Div0\|lpm_divide_vcm:auto_generated\|sign_div_unsign_9kh:divider\|alt_u_div_kve:divider\|add_sub_5_result_int\[5\]~27'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.410 ns" { MinClkGen:MCG1|lpm_divide:Div0|lpm_divide_vcm:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|add_sub_5_result_int[4]~26 MinClkGen:MCG1|lpm_divide:Div0|lpm_divide_vcm:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|add_sub_5_result_int[5]~27 } "NODE_NAME" } } { "db/alt_u_div_kve.tdf" "" { Text "D:/PROGRAMING/fpga/Time/db/alt_u_div_kve.tdf" 52 22 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.556 ns) + CELL(0.150 ns) 10.083 ns DecDis:MC1\|WideOr5~28 13 COMB LCCOMB_X32_Y18_N26 1 " "Info: 13: + IC(1.556 ns) + CELL(0.150 ns) = 10.083 ns; Loc. = LCCOMB_X32_Y18_N26; Fanout = 1; COMB Node = 'DecDis:MC1\|WideOr5~28'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.706 ns" { MinClkGen:MCG1|lpm_divide:Div0|lpm_divide_vcm:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|add_sub_5_result_int[5]~27 DecDis:MC1|WideOr5~28 } "NODE_NAME" } } { "Time.v" "" { Text "D:/PROGRAMING/fpga/Time/Time.v" 41 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 10.167 ns DecDis:MC1\|HexVal\[1\] 14 REG LCFF_X32_Y18_N27 1 " "Info: 14: + IC(0.000 ns) + CELL(0.084 ns) = 10.167 ns; Loc. = LCFF_X32_Y18_N27; Fanout = 1; REG Node = 'DecDis:MC1\|HexVal\[1\]'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.084 ns" { DecDis:MC1|WideOr5~28 DecDis:MC1|HexVal[1] } "NODE_NAME" } } { "Time.v" "" { Text "D:/PROGRAMING/fpga/Time/Time.v" 41 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.369 ns ( 33.14 % ) " "Info: Total cell delay = 3.369 ns ( 33.14 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.798 ns ( 66.86 % ) " "Info: Total interconnect delay = 6.798 ns ( 66.86 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "10.167 ns" { MinClkGen:MCG1|countm[3] MinClkGen:MCG1|lpm_divide:Div0|lpm_divide_vcm:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|add_sub_3_result_int[1]~15 MinClkGen:MCG1|lpm_divide:Div0|lpm_divide_vcm:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|add_sub_3_result_int[2]~17 MinClkGen:MCG1|lpm_divide:Div0|lpm_divide_vcm:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|add_sub_3_result_int[3]~19 MinClkGen:MCG1|lpm_divide:Div0|lpm_divide_vcm:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|add_sub_3_result_int[4]~20 MinClkGen:MCG1|lpm_divide:Div0|lpm_divide_vcm:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|StageOut[18]~21 MinClkGen:MCG1|lpm_divide:Div0|lpm_divide_vcm:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|add_sub_4_result_int[4]~23 MinClkGen:MCG1|lpm_divide:Div0|lpm_divide_vcm:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|add_sub_4_result_int[5]~24 MinClkGen:MCG1|lpm_divide:Div0|lpm_divide_vcm:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|StageOut[22]~276 MinClkGen:MCG1|lpm_divide:Div0|lpm_divide_vcm:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|add_sub_5_result_int[3]~24 MinClkGen:MCG1|lpm_divide:Div0|lpm_divide_vcm:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|add_sub_5_result_int[4]~26 MinClkGen:MCG1|lpm_divide:Div0|lpm_divide_vcm:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|add_sub_5_result_int[5]~27 DecDis:MC1|WideOr5~28 DecDis:MC1|HexVal[1] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "10.167 ns" { MinClkGen:MCG1|countm[3] {} MinClkGen:MCG1|lpm_divide:Div0|lpm_divide_vcm:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|add_sub_3_result_int[1]~15 {} MinClkGen:MCG1|lpm_divide:Div0|lpm_divide_vcm:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|add_sub_3_result_int[2]~17 {} MinClkGen:MCG1|lpm_divide:Div0|lpm_divide_vcm:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|add_sub_3_result_int[3]~19 {} MinClkGen:MCG1|lpm_divide:Div0|lpm_divide_vcm:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|add_sub_3_result_int[4]~20 {} MinClkGen:MCG1|lpm_divide:Div0|lpm_divide_vcm:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|StageOut[18]~21 {} MinClkGen:MCG1|lpm_divide:Div0|lpm_divide_vcm:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|add_sub_4_result_int[4]~23 {} MinClkGen:MCG1|lpm_divide:Div0|lpm_divide_vcm:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|add_sub_4_result_int[5]~24 {} MinClkGen:MCG1|lpm_divide:Div0|lpm_divide_vcm:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|StageOut[22]~276 {} MinClkGen:MCG1|lpm_divide:Div0|lpm_divide_vcm:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|add_sub_5_result_int[3]~24 {} MinClkGen:MCG1|lpm_divide:Div0|lpm_divide_vcm:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|add_sub_5_result_int[4]~26 {} MinClkGen:MCG1|lpm_divide:Div0|lpm_divide_vcm:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|add_sub_5_result_int[5]~27 {} DecDis:MC1|WideOr5~28 {} DecDis:MC1|HexVal[1] {} } { 0.000ns 0.524ns 0.000ns 0.000ns 0.000ns 1.744ns 1.499ns 0.000ns 0.731ns 0.744ns 0.000ns 0.000ns 1.556ns 0.000ns } { 0.000ns 0.393ns 0.071ns 0.159ns 0.410ns 0.150ns 0.393ns 0.410ns 0.275ns 0.393ns 0.071ns 0.410ns 0.150ns 0.084ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "3.910 ns - Smallest " "Info: - Smallest clock skew is 3.910 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK_50 destination 6.591 ns + Shortest register " "Info: + Shortest clock path from clock \"CLOCK_50\" to destination register is 6.591 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns CLOCK_50 1 CLK PIN_N2 2 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 2; CLK Node = 'CLOCK_50'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "Time.v" "" { Text "D:/PROGRAMING/fpga/Time/Time.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.245 ns) + CELL(0.787 ns) 3.031 ns SecClkGen:SCG1\|countc\[24\] 2 REG LCFF_X30_Y18_N31 5 " "Info: 2: + IC(1.245 ns) + CELL(0.787 ns) = 3.031 ns; Loc. = LCFF_X30_Y18_N31; Fanout = 5; REG Node = 'SecClkGen:SCG1\|countc\[24\]'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.032 ns" { CLOCK_50 SecClkGen:SCG1|countc[24] } "NODE_NAME" } } { "Time.v" "" { Text "D:/PROGRAMING/fpga/Time/Time.v" 74 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.971 ns) + CELL(0.000 ns) 5.002 ns SecClkGen:SCG1\|countc\[24\]~clkctrl 3 COMB CLKCTRL_G13 41 " "Info: 3: + IC(1.971 ns) + CELL(0.000 ns) = 5.002 ns; Loc. = CLKCTRL_G13; Fanout = 41; COMB Node = 'SecClkGen:SCG1\|countc\[24\]~clkctrl'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.971 ns" { SecClkGen:SCG1|countc[24] SecClkGen:SCG1|countc[24]~clkctrl } "NODE_NAME" } } { "Time.v" "" { Text "D:/PROGRAMING/fpga/Time/Time.v" 74 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.052 ns) + CELL(0.537 ns) 6.591 ns DecDis:MC1\|HexVal\[1\] 4 REG LCFF_X32_Y18_N27 1 " "Info: 4: + IC(1.052 ns) + CELL(0.537 ns) = 6.591 ns; Loc. = LCFF_X32_Y18_N27; Fanout = 1; REG Node = 'DecDis:MC1\|HexVal\[1\]'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.589 ns" { SecClkGen:SCG1|countc[24]~clkctrl DecDis:MC1|HexVal[1] } "NODE_NAME" } } { "Time.v" "" { Text "D:/PROGRAMING/fpga/Time/Time.v" 41 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.323 ns ( 35.25 % ) " "Info: Total cell delay = 2.323 ns ( 35.25 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.268 ns ( 64.75 % ) " "Info: Total interconnect delay = 4.268 ns ( 64.75 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.591 ns" { CLOCK_50 SecClkGen:SCG1|countc[24] SecClkGen:SCG1|countc[24]~clkctrl DecDis:MC1|HexVal[1] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.591 ns" { CLOCK_50 {} CLOCK_50~combout {} SecClkGen:SCG1|countc[24] {} SecClkGen:SCG1|countc[24]~clkctrl {} DecDis:MC1|HexVal[1] {} } { 0.000ns 0.000ns 1.245ns 1.971ns 1.052ns } { 0.000ns 0.999ns 0.787ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK_50 source 2.681 ns - Longest register " "Info: - Longest clock path from clock \"CLOCK_50\" to source register is 2.681 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns CLOCK_50 1 CLK PIN_N2 2 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 2; CLK Node = 'CLOCK_50'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "Time.v" "" { Text "D:/PROGRAMING/fpga/Time/Time.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns CLOCK_50~clkctrl 2 COMB CLKCTRL_G2 74 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 74; COMB Node = 'CLOCK_50~clkctrl'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.118 ns" { CLOCK_50 CLOCK_50~clkctrl } "NODE_NAME" } } { "Time.v" "" { Text "D:/PROGRAMING/fpga/Time/Time.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.027 ns) + CELL(0.537 ns) 2.681 ns MinClkGen:MCG1\|countm\[3\] 3 REG LCFF_X54_Y21_N23 11 " "Info: 3: + IC(1.027 ns) + CELL(0.537 ns) = 2.681 ns; Loc. = LCFF_X54_Y21_N23; Fanout = 11; REG Node = 'MinClkGen:MCG1\|countm\[3\]'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.564 ns" { CLOCK_50~clkctrl MinClkGen:MCG1|countm[3] } "NODE_NAME" } } { "Time.v" "" { Text "D:/PROGRAMING/fpga/Time/Time.v" 101 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.29 % ) " "Info: Total cell delay = 1.536 ns ( 57.29 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.145 ns ( 42.71 % ) " "Info: Total interconnect delay = 1.145 ns ( 42.71 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.681 ns" { CLOCK_50 CLOCK_50~clkctrl MinClkGen:MCG1|countm[3] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.681 ns" { CLOCK_50 {} CLOCK_50~combout {} CLOCK_50~clkctrl {} MinClkGen:MCG1|countm[3] {} } { 0.000ns 0.000ns 0.118ns 1.027ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.591 ns" { CLOCK_50 SecClkGen:SCG1|countc[24] SecClkGen:SCG1|countc[24]~clkctrl DecDis:MC1|HexVal[1] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.591 ns" { CLOCK_50 {} CLOCK_50~combout {} SecClkGen:SCG1|countc[24] {} SecClkGen:SCG1|countc[24]~clkctrl {} DecDis:MC1|HexVal[1] {} } { 0.000ns 0.000ns 1.245ns 1.971ns 1.052ns } { 0.000ns 0.999ns 0.787ns 0.000ns 0.537ns } "" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.681 ns" { CLOCK_50 CLOCK_50~clkctrl MinClkGen:MCG1|countm[3] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.681 ns" { CLOCK_50 {} CLOCK_50~combout {} CLOCK_50~clkctrl {} MinClkGen:MCG1|countm[3] {} } { 0.000ns 0.000ns 0.118ns 1.027ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "Time.v" "" { Text "D:/PROGRAMING/fpga/Time/Time.v" 101 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "Time.v" "" { Text "D:/PROGRAMING/fpga/Time/Time.v" 41 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "10.167 ns" { MinClkGen:MCG1|countm[3] MinClkGen:MCG1|lpm_divide:Div0|lpm_divide_vcm:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|add_sub_3_result_int[1]~15 MinClkGen:MCG1|lpm_divide:Div0|lpm_divide_vcm:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|add_sub_3_result_int[2]~17 MinClkGen:MCG1|lpm_divide:Div0|lpm_divide_vcm:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|add_sub_3_result_int[3]~19 MinClkGen:MCG1|lpm_divide:Div0|lpm_divide_vcm:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|add_sub_3_result_int[4]~20 MinClkGen:MCG1|lpm_divide:Div0|lpm_divide_vcm:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|StageOut[18]~21 MinClkGen:MCG1|lpm_divide:Div0|lpm_divide_vcm:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|add_sub_4_result_int[4]~23 MinClkGen:MCG1|lpm_divide:Div0|lpm_divide_vcm:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|add_sub_4_result_int[5]~24 MinClkGen:MCG1|lpm_divide:Div0|lpm_divide_vcm:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|StageOut[22]~276 MinClkGen:MCG1|lpm_divide:Div0|lpm_divide_vcm:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|add_sub_5_result_int[3]~24 MinClkGen:MCG1|lpm_divide:Div0|lpm_divide_vcm:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|add_sub_5_result_int[4]~26 MinClkGen:MCG1|lpm_divide:Div0|lpm_divide_vcm:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|add_sub_5_result_int[5]~27 DecDis:MC1|WideOr5~28 DecDis:MC1|HexVal[1] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "10.167 ns" { MinClkGen:MCG1|countm[3] {} MinClkGen:MCG1|lpm_divide:Div0|lpm_divide_vcm:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|add_sub_3_result_int[1]~15 {} MinClkGen:MCG1|lpm_divide:Div0|lpm_divide_vcm:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|add_sub_3_result_int[2]~17 {} MinClkGen:MCG1|lpm_divide:Div0|lpm_divide_vcm:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|add_sub_3_result_int[3]~19 {} MinClkGen:MCG1|lpm_divide:Div0|lpm_divide_vcm:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|add_sub_3_result_int[4]~20 {} MinClkGen:MCG1|lpm_divide:Div0|lpm_divide_vcm:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|StageOut[18]~21 {} MinClkGen:MCG1|lpm_divide:Div0|lpm_divide_vcm:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|add_sub_4_result_int[4]~23 {} MinClkGen:MCG1|lpm_divide:Div0|lpm_divide_vcm:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|add_sub_4_result_int[5]~24 {} MinClkGen:MCG1|lpm_divide:Div0|lpm_divide_vcm:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|StageOut[22]~276 {} MinClkGen:MCG1|lpm_divide:Div0|lpm_divide_vcm:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|add_sub_5_result_int[3]~24 {} MinClkGen:MCG1|lpm_divide:Div0|lpm_divide_vcm:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|add_sub_5_result_int[4]~26 {} MinClkGen:MCG1|lpm_divide:Div0|lpm_divide_vcm:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|add_sub_5_result_int[5]~27 {} DecDis:MC1|WideOr5~28 {} DecDis:MC1|HexVal[1] {} } { 0.000ns 0.524ns 0.000ns 0.000ns 0.000ns 1.744ns 1.499ns 0.000ns 0.731ns 0.744ns 0.000ns 0.000ns 1.556ns 0.000ns } { 0.000ns 0.393ns 0.071ns 0.159ns 0.410ns 0.150ns 0.393ns 0.410ns 0.275ns 0.393ns 0.071ns 0.410ns 0.150ns 0.084ns } "" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.591 ns" { CLOCK_50 SecClkGen:SCG1|countc[24] SecClkGen:SCG1|countc[24]~clkctrl DecDis:MC1|HexVal[1] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.591 ns" { CLOCK_50 {} CLOCK_50~combout {} SecClkGen:SCG1|countc[24] {} SecClkGen:SCG1|countc[24]~clkctrl {} DecDis:MC1|HexVal[1] {} } { 0.000ns 0.000ns 1.245ns 1.971ns 1.052ns } { 0.000ns 0.999ns 0.787ns 0.000ns 0.537ns } "" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.681 ns" { CLOCK_50 CLOCK_50~clkctrl MinClkGen:MCG1|countm[3] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.681 ns" { CLOCK_50 {} CLOCK_50~combout {} CLOCK_50~clkctrl {} MinClkGen:MCG1|countm[3] {} } { 0.000ns 0.000ns 0.118ns 1.027ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}