time.tan.qmsg

ALTERA上DE2平台

{ "Info" "ITDB_TSU_RESULT" "MinClkGen:MCG1\|countm\[0\] SW\[17\] CLOCK_50 7.131 ns register " "Info: tsu for register \"MinClkGen:MCG1\|countm\[0\]\" (data pin = \"SW\[17\]\", clock pin = \"CLOCK_50\") is 7.131 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.845 ns + Longest pin register " "Info: + Longest pin to register delay is 9.845 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.852 ns) 0.852 ns SW\[17\] 1 PIN PIN_V2 102 " "Info: 1: + IC(0.000 ns) + CELL(0.852 ns) = 0.852 ns; Loc. = PIN_V2; Fanout = 102; PIN Node = 'SW\[17\]'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { SW[17] } "NODE_NAME" } } { "Time.v" "" { Text "D:/PROGRAMING/fpga/Time/Time.v" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(6.525 ns) + CELL(0.371 ns) 7.748 ns MinClkGen:MCG1\|countm\[0\]~356 2 COMB LCCOMB_X31_Y19_N6 6 " "Info: 2: + IC(6.525 ns) + CELL(0.371 ns) = 7.748 ns; Loc. = LCCOMB_X31_Y19_N6; Fanout = 6; COMB Node = 'MinClkGen:MCG1\|countm\[0\]~356'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.896 ns" { SW[17] MinClkGen:MCG1|countm[0]~356 } "NODE_NAME" } } { "Time.v" "" { Text "D:/PROGRAMING/fpga/Time/Time.v" 101 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.437 ns) + CELL(0.660 ns) 9.845 ns MinClkGen:MCG1\|countm\[0\] 3 REG LCFF_X54_Y22_N3 13 " "Info: 3: + IC(1.437 ns) + CELL(0.660 ns) = 9.845 ns; Loc. = LCFF_X54_Y22_N3; Fanout = 13; REG Node = 'MinClkGen:MCG1\|countm\[0\]'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.097 ns" { MinClkGen:MCG1|countm[0]~356 MinClkGen:MCG1|countm[0] } "NODE_NAME" } } { "Time.v" "" { Text "D:/PROGRAMING/fpga/Time/Time.v" 101 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.883 ns ( 19.13 % ) " "Info: Total cell delay = 1.883 ns ( 19.13 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.962 ns ( 80.87 % ) " "Info: Total interconnect delay = 7.962 ns ( 80.87 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "9.845 ns" { SW[17] MinClkGen:MCG1|countm[0]~356 MinClkGen:MCG1|countm[0] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "9.845 ns" { SW[17] {} SW[17]~combout {} MinClkGen:MCG1|countm[0]~356 {} MinClkGen:MCG1|countm[0] {} } { 0.000ns 0.000ns 6.525ns 1.437ns } { 0.000ns 0.852ns 0.371ns 0.660ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "Time.v" "" { Text "D:/PROGRAMING/fpga/Time/Time.v" 101 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK_50 destination 2.678 ns - Shortest register " "Info: - Shortest clock path from clock \"CLOCK_50\" to destination register is 2.678 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns CLOCK_50 1 CLK PIN_N2 2 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 2; CLK Node = 'CLOCK_50'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "Time.v" "" { Text "D:/PROGRAMING/fpga/Time/Time.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns CLOCK_50~clkctrl 2 COMB CLKCTRL_G2 74 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 74; COMB Node = 'CLOCK_50~clkctrl'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.118 ns" { CLOCK_50 CLOCK_50~clkctrl } "NODE_NAME" } } { "Time.v" "" { Text "D:/PROGRAMING/fpga/Time/Time.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.024 ns) + CELL(0.537 ns) 2.678 ns MinClkGen:MCG1\|countm\[0\] 3 REG LCFF_X54_Y22_N3 13 " "Info: 3: + IC(1.024 ns) + CELL(0.537 ns) = 2.678 ns; Loc. = LCFF_X54_Y22_N3; Fanout = 13; REG Node = 'MinClkGen:MCG1\|countm\[0\]'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.561 ns" { CLOCK_50~clkctrl MinClkGen:MCG1|countm[0] } "NODE_NAME" } } { "Time.v" "" { Text "D:/PROGRAMING/fpga/Time/Time.v" 101 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.36 % ) " "Info: Total cell delay = 1.536 ns ( 57.36 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.142 ns ( 42.64 % ) " "Info: Total interconnect delay = 1.142 ns ( 42.64 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.678 ns" { CLOCK_50 CLOCK_50~clkctrl MinClkGen:MCG1|countm[0] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.678 ns" { CLOCK_50 {} CLOCK_50~combout {} CLOCK_50~clkctrl {} MinClkGen:MCG1|countm[0] {} } { 0.000ns 0.000ns 0.118ns 1.024ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "9.845 ns" { SW[17] MinClkGen:MCG1|countm[0]~356 MinClkGen:MCG1|countm[0] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "9.845 ns" { SW[17] {} SW[17]~combout {} MinClkGen:MCG1|countm[0]~356 {} MinClkGen:MCG1|countm[0] {} } { 0.000ns 0.000ns 6.525ns 1.437ns } { 0.000ns 0.852ns 0.371ns 0.660ns } "" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.678 ns" { CLOCK_50 CLOCK_50~clkctrl MinClkGen:MCG1|countm[0] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.678 ns" { CLOCK_50 {} CLOCK_50~combout {} CLOCK_50~clkctrl {} MinClkGen:MCG1|countm[0] {} } { 0.000ns 0.000ns 0.118ns 1.024ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLOCK_50 LEDG\[3\] SecClkGen:SCG1\|counts\[3\] 14.258 ns register " "Info: tco from clock \"CLOCK_50\" to destination pin \"LEDG\[3\]\" through register \"SecClkGen:SCG1\|counts\[3\]\" is 14.258 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK_50 source 2.675 ns + Longest register " "Info: + Longest clock path from clock \"CLOCK_50\" to source register is 2.675 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns CLOCK_50 1 CLK PIN_N2 2 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 2; CLK Node = 'CLOCK_50'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "Time.v" "" { Text "D:/PROGRAMING/fpga/Time/Time.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns CLOCK_50~clkctrl 2 COMB CLKCTRL_G2 74 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 74; COMB Node = 'CLOCK_50~clkctrl'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.118 ns" { CLOCK_50 CLOCK_50~clkctrl } "NODE_NAME" } } { "Time.v" "" { Text "D:/PROGRAMING/fpga/Time/Time.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.021 ns) + CELL(0.537 ns) 2.675 ns SecClkGen:SCG1\|counts\[3\] 3 REG LCFF_X55_Y7_N1 14 " "Info: 3: + IC(1.021 ns) + CELL(0.537 ns) = 2.675 ns; Loc. = LCFF_X55_Y7_N1; Fanout = 14; REG Node = 'SecClkGen:SCG1\|counts\[3\]'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.558 ns" { CLOCK_50~clkctrl SecClkGen:SCG1|counts[3] } "NODE_NAME" } } { "Time.v" "" { Text "D:/PROGRAMING/fpga/Time/Time.v" 74 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.42 % ) " "Info: Total cell delay = 1.536 ns ( 57.42 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.139 ns ( 42.58 % ) " "Info: Total interconnect delay = 1.139 ns ( 42.58 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.675 ns" { CLOCK_50 CLOCK_50~clkctrl SecClkGen:SCG1|counts[3] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.675 ns" { CLOCK_50 {} CLOCK_50~combout {} CLOCK_50~clkctrl {} SecClkGen:SCG1|counts[3] {} } { 0.000ns 0.000ns 0.118ns 1.021ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "Time.v" "" { Text "D:/PROGRAMING/fpga/Time/Time.v" 74 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.333 ns + Longest register pin " "Info: + Longest register to pin delay is 11.333 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns SecClkGen:SCG1\|counts\[3\] 1 REG LCFF_X55_Y7_N1 14 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X55_Y7_N1; Fanout = 14; REG Node = 'SecClkGen:SCG1\|counts\[3\]'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { SecClkGen:SCG1|counts[3] } "NODE_NAME" } } { "Time.v" "" { Text "D:/PROGRAMING/fpga/Time/Time.v" 74 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.323 ns) + CELL(0.393 ns) 0.716 ns SecClkGen:SCG1\|lpm_divide:Mod0\|lpm_divide_25m:auto_generated\|sign_div_unsign_9kh:divider\|alt_u_div_kve:divider\|add_sub_3_result_int\[1\]~11 2 COMB LCCOMB_X55_Y7_N8 2 " "Info: 2: + IC(0.323 ns) + CELL(0.393 ns) = 0.716 ns; Loc. = LCCOMB_X55_Y7_N8; Fanout = 2; COMB Node = 'SecClkGen:SCG1\|lpm_divide:Mod0\|lpm_divide_25m:auto_generated\|sign_div_unsign_9kh:divider\|alt_u_div_kve:divider\|add_sub_3_result_int\[1\]~11'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.716 ns" { SecClkGen:SCG1|counts[3] SecClkGen:SCG1|lpm_divide:Mod0|lpm_divide_25m:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|add_sub_3_result_int[1]~11 } "NODE_NAME" } } { "db/alt_u_div_kve.tdf" "" { Text "D:/PROGRAMING/fpga/Time/db/alt_u_div_kve.tdf" 42 22 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 0.787 ns SecClkGen:SCG1\|lpm_divide:Mod0\|lpm_divide_25m:auto_generated\|sign_div_unsign_9kh:divider\|alt_u_div_kve:divider\|add_sub_3_result_int\[2\]~13 3 COMB LCCOMB_X55_Y7_N10 2 " "Info: 3: + IC(0.000 ns) + CELL(0.071 ns) = 0.787 ns; Loc. = LCCOMB_X55_Y7_N10; Fanout = 2; COMB Node = 'SecClkGen:SCG1\|lpm_divide:Mod0\|lpm_divide_25m:auto_generated\|sign_div_unsign_9kh:divider\|alt_u_div_kve:divider\|add_sub_3_result_int\[2\]~13'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { SecClkGen:SCG1|lpm_divide:Mod0|lpm_divide_25m:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|add_sub_3_result_int[1]~11 SecClkGen:SCG1|lpm_divide:Mod0|lpm_divide_25m:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|add_sub_3_result_int[2]~13 } "NODE_NAME" } } { "db/alt_u_div_kve.tdf" "" { Text "D:/PROGRAMING/fpga/Time/db/alt_u_div_kve.tdf" 42 22 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 0.858 ns SecClkGen:SCG1\|lpm_divide:Mod0\|lpm_divide_25m:auto_generated\|sign_div_unsign_9kh:divider\|alt_u_div_kve:divider\|add_sub_3_result_int\[3\]~15 4 COMB LCCOMB_X55_Y7_N12 1 " "Info: 4: + IC(0.000 ns) + CELL(0.071 ns) = 0.858 ns; Loc. = LCCOMB_X55_Y7_N12; Fanout = 1; COMB Node = 'SecClkGen:SCG1\|lpm_divide:Mod0\|lpm_divide_25m:auto_generated\|sign_div_unsign_9kh:divider\|alt_u_div_kve:divider\|add_sub_3_result_int\[3\]~15'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { SecClkGen:SCG1|lpm_divide:Mod0|lpm_divide_25m:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|add_sub_3_result_int[2]~13 SecClkGen:SCG1|lpm_divide:Mod0|lpm_divide_25m:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|add_sub_3_result_int[3]~15 } "NODE_NAME" } } { "db/alt_u_div_kve.tdf" "" { Text "D:/PROGRAMING/fpga/Time/db/alt_u_div_kve.tdf" 42 22 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.410 ns) 1.268 ns SecClkGen:SCG1\|lpm_divide:Mod0\|lpm_divide_25m:auto_generated\|sign_div_unsign_9kh:divider\|alt_u_div_kve:divider\|add_sub_3_result_int\[4\]~16 5 COMB LCCOMB_X55_Y7_N14 10 " "Info: 5: + IC(0.000 ns) + CELL(0.410 ns) = 1.268 ns; Loc. = LCCOMB_X55_Y7_N14; Fanout = 10; COMB Node = 'SecClkGen:SCG1\|lpm_divide:Mod0\|lpm_divide_25m:auto_generated\|sign_div_unsign_9kh:divider\|alt_u_div_kve:divider\|add_sub_3_result_int\[4\]~16'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.410 ns" { SecClkGen:SCG1|lpm_divide:Mod0|lpm_divide_25m:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|add_sub_3_result_int[3]~15 SecClkGen:SCG1|lpm_divide:Mod0|lpm_divide_25m:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|add_sub_3_result_int[4]~16 } "NODE_NAME" } } { "db/alt_u_div_kve.tdf" "" { Text "D:/PROGRAMING/fpga/Time/db/alt_u_div_kve.tdf" 42 22 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.813 ns) + CELL(0.150 ns) 2.231 ns SecClkGen:SCG1\|lpm_divide:Mod0\|lpm_divide_25m:auto_generated\|sign_div_unsign_9kh:divider\|alt_u_div_kve:divider\|StageOut\[16\]~23 6 COMB LCCOMB_X55_Y6_N12 2 " "Info: 6: + IC(0.813 ns) + CELL(0.150 ns) = 2.231 ns; Loc. = LCCOMB_X55_Y6_N12; Fanout = 2; COMB Node = 'SecClkGen:SCG1\|lpm_divide:Mod0\|lpm_divide_25m:auto_generated\|sign_div_unsign_9kh:divider\|alt_u_div_kve:divider\|StageOut\[16\]~23'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.963 ns" { SecClkGen:SCG1|lpm_divide:Mod0|lpm_divide_25m:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|add_sub_3_result_int[4]~16 SecClkGen:SCG1|lpm_divide:Mod0|lpm_divide_25m:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_kve:divider|StageOut[16]~23 } "NODE_NAME" } } { "db/alt_u_div_kve.tdf" "" { Text "D:/PROGRAMING/fpga/Time/db/alt_u_div_kve.tdf" 69 10 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.731 ns) + CELL(0.414 ns) 3.376 ns SecClkGen:SCG1\|lpm_divide:Mod0\|lpm_divide_25m:auto_generated\|sign_div_unsign_9kh:divider\|alt_u_div_kve:divider\|add_sub_4_result_int\[2\]~15 7 COMB LCCOMB_X55_Y7_N22 2 " "Info: 7: + IC(0.731 ns) + CELL(0.414 ns) = 3.376 ns; Loc. = LCCOMB_X55_Y7_N22; Fanout = 2; COMB Node = 'SecClkGen:SCG1\|lpm_divide:Mod0\|lpm_divide_25m:auto_generated\|sign_div_unsign_9kh:divider\|alt_u_div_kve:divider\|add_sub_4_result_int\[2\]~15'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/