time.tan.rpt

ALTERA上DE2平台

; Cut off read during write signal paths                         ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                                 ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                               ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                          ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements                        ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                               ; Off                ;      ;    ;             ;
; Enable Clock Latency                                           ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                                  ; Off                ;      ;    ;             ;
; Number of source nodes to report per destination node          ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                          ; 10                 ;      ;    ;             ;
; Number of paths to report                                      ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                                   ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                         ; Off                ;      ;    ;             ;
; Report IO Paths Separately                                     ; Off                ;      ;    ;             ;
; Perform Multicorner Analysis                                   ; On                 ;      ;    ;             ;
; Reports the worst-case path for each clock domain and analysis ; Off                ;      ;    ;             ;
+----------------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; CLOCK_50        ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'CLOCK_50'                                                                                                                                                                                                                                           ;
+-----------------------------------------+-----------------------------------------------------+---------------------------+---------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                      ; To                        ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+---------------------------+---------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; 154.54 MHz ( period = 6.471 ns )                    ; MinClkGen:MCG1|countm[3]  ; DecDis:MC1|HexVal[1]      ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 10.167 ns               ;
; N/A                                     ; 154.56 MHz ( period = 6.470 ns )                    ; MinClkGen:MCG1|countm[3]  ; DecDis:MC1|HexVal[2]      ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 10.166 ns               ;
; N/A                                     ; 155.81 MHz ( period = 6.418 ns )                    ; MinClkGen:MCG1|countm[4]  ; DecDis:MC1|HexVal[1]      ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 10.114 ns               ;
; N/A                                     ; 155.84 MHz ( period = 6.417 ns )                    ; MinClkGen:MCG1|countm[4]  ; DecDis:MC1|HexVal[2]      ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 10.113 ns               ;
; N/A                                     ; 157.01 MHz ( period = 6.369 ns )                    ; MinClkGen:MCG1|countm[5]  ; DecDis:MC1|HexVal[1]      ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 10.065 ns               ;
; N/A                                     ; 157.04 MHz ( period = 6.368 ns )                    ; MinClkGen:MCG1|countm[5]  ; DecDis:MC1|HexVal[2]      ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 10.064 ns               ;
; N/A                                     ; 164.07 MHz ( period = 6.095 ns )                    ; SecClkGen:SCG1|countc[1]  ; MinClkGen:MCG1|countm[0]  ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 5.861 ns                ;
; N/A                                     ; 164.07 MHz ( period = 6.095 ns )                    ; SecClkGen:SCG1|countc[1]  ; MinClkGen:MCG1|countm[1]  ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 5.861 ns                ;
; N/A                                     ; 164.07 MHz ( period = 6.095 ns )                    ; SecClkGen:SCG1|countc[1]  ; MinClkGen:MCG1|countm[2]  ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 5.861 ns                ;
; N/A                                     ; 164.12 MHz ( period = 6.093 ns )                    ; SecClkGen:SCG1|countc[18] ; MinClkGen:MCG1|countm[0]  ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 5.859 ns                ;
; N/A                                     ; 164.12 MHz ( period = 6.093 ns )                    ; SecClkGen:SCG1|countc[18] ; MinClkGen:MCG1|countm[1]  ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 5.859 ns                ;
; N/A                                     ; 164.12 MHz ( period = 6.093 ns )                    ; SecClkGen:SCG1|countc[18] ; MinClkGen:MCG1|countm[2]  ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 5.859 ns                ;
; N/A                                     ; 164.34 MHz ( period = 6.085 ns )                    ; SecClkGen:SCG1|countc[3]  ; MinClkGen:MCG1|countm[0]  ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 5.851 ns                ;
; N/A                                     ; 164.34 MHz ( period = 6.085 ns )                    ; SecClkGen:SCG1|countc[3]  ; MinClkGen:MCG1|countm[1]  ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 5.851 ns                ;
; N/A                                     ; 164.34 MHz ( period = 6.085 ns )                    ; SecClkGen:SCG1|countc[3]  ; MinClkGen:MCG1|countm[2]  ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 5.851 ns                ;
; N/A                                     ; 164.42 MHz ( period = 6.082 ns )                    ; SecClkGen:SCG1|countc[1]  ; MinClkGen:MCG1|countm[3]  ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 5.851 ns                ;
; N/A                                     ; 164.42 MHz ( period = 6.082 ns )                    ; SecClkGen:SCG1|countc[1]  ; MinClkGen:MCG1|countm[4]  ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 5.851 ns                ;
; N/A                                     ; 164.42 MHz ( period = 6.082 ns )                    ; SecClkGen:SCG1|countc[1]  ; MinClkGen:MCG1|countm[5]  ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 5.851 ns                ;
; N/A                                     ; 164.47 MHz ( period = 6.080 ns )                    ; SecClkGen:SCG1|countc[18] ; MinClkGen:MCG1|countm[3]  ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 5.849 ns                ;
; N/A                                     ; 164.47 MHz ( period = 6.080 ns )                    ; SecClkGen:SCG1|countc[18] ; MinClkGen:MCG1|countm[4]  ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 5.849 ns                ;
; N/A                                     ; 164.47 MHz ( period = 6.080 ns )                    ; SecClkGen:SCG1|countc[18] ; MinClkGen:MCG1|countm[5]  ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 5.849 ns                ;
; N/A                                     ; 164.69 MHz ( period = 6.072 ns )                    ; SecClkGen:SCG1|countc[3]  ; MinClkGen:MCG1|countm[3]  ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 5.841 ns                ;
; N/A                                     ; 164.69 MHz ( period = 6.072 ns )                    ; SecClkGen:SCG1|countc[3]  ; MinClkGen:MCG1|countm[4]  ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 5.841 ns                ;
; N/A                                     ; 164.69 MHz ( period = 6.072 ns )                    ; SecClkGen:SCG1|countc[3]  ; MinClkGen:MCG1|countm[5]  ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 5.841 ns                ;
; N/A                                     ; 164.83 MHz ( period = 6.067 ns )                    ; SecClkGen:SCG1|countc[2]  ; MinClkGen:MCG1|countm[0]  ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 5.833 ns                ;
; N/A                                     ; 164.83 MHz ( period = 6.067 ns )                    ; SecClkGen:SCG1|countc[2]  ; MinClkGen:MCG1|countm[1]  ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 5.833 ns                ;
; N/A                                     ; 164.83 MHz ( period = 6.067 ns )                    ; SecClkGen:SCG1|countc[2]  ; MinClkGen:MCG1|countm[2]  ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 5.833 ns                ;
; N/A                                     ; 165.18 MHz ( period = 6.054 ns )                    ; SecClkGen:SCG1|countc[2]  ; MinClkGen:MCG1|countm[3]  ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 5.823 ns                ;
; N/A                                     ; 165.18 MHz ( period = 6.054 ns )                    ; SecClkGen:SCG1|countc[2]  ; MinClkGen:MCG1|countm[4]  ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 5.823 ns                ;
; N/A                                     ; 165.18 MHz ( period = 6.054 ns )                    ; SecClkGen:SCG1|countc[2]  ; MinClkGen:MCG1|countm[5]  ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 5.823 ns                ;