📄 time.map.rpt
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; Quartus II Version ; 7.2 Build 207 03/18/2008 SP 3 SJ Full Version ;
; Revision Name ; Time ;
; Top-level Entity Name ; Time ;
; Family ; Cyclone II ;
; Total logic elements ; N/A until Partition Merge ;
; Total combinational functions ; N/A until Partition Merge ;
; Dedicated logic registers ; N/A until Partition Merge ;
; Total registers ; N/A until Partition Merge ;
; Total pins ; N/A until Partition Merge ;
; Total virtual pins ; N/A until Partition Merge ;
; Total memory bits ; N/A until Partition Merge ;
; Embedded Multiplier 9-bit elements ; N/A until Partition Merge ;
; Total PLLs ; N/A until Partition Merge ;
+------------------------------------+-----------------------------------------------+
+--------------------------------------------------------------------------------------------------------------------------+
; Analysis & Elaboration Settings ;
+--------------------------------------------------------------------------------+--------------------+--------------------+
; Option ; Setting ; Default Value ;
+--------------------------------------------------------------------------------+--------------------+--------------------+
; Device ; EP2C35F672C6 ; ;
; Top-level entity name ; Time ; Time ;
; Family name ; Cyclone II ; Stratix II ;
; Use Generated Physical Constraints File ; Off ; ;
; Use smart compilation ; Off ; Off ;
; Maximum processors allowed for parallel compilation ; 1 ; 1 ;
; Restructure Multiplexers ; Auto ; Auto ;
; Create Debugging Nodes for IP Cores ; Off ; Off ;
; Preserve fewer node names ; On ; On ;
; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
; VHDL Version ; VHDL93 ; VHDL93 ;
; State Machine Processing ; Auto ; Auto ;
; Safe State Machine ; Off ; Off ;
; Extract Verilog State Machines ; On ; On ;
; Extract VHDL State Machines ; On ; On ;
; Ignore Verilog initial constructs ; Off ; Off ;
; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
; Parallel Synthesis ; Off ; Off ;
; DSP Block Balancing ; Auto ; Auto ;
; NOT Gate Push-Back ; On ; On ;
; Power-Up Don't Care ; On ; On ;
; Remove Redundant Logic Cells ; Off ; Off ;
; Remove Duplicate Registers ; On ; On ;
; Ignore CARRY Buffers ; Off ; Off ;
; Ignore CASCADE Buffers ; Off ; Off ;
; Ignore GLOBAL Buffers ; Off ; Off ;
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
; Ignore LCELL Buffers ; Off ; Off ;
; Ignore SOFT Buffers ; On ; On ;
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
; Optimization Technique -- Cyclone II/Cyclone III ; Balanced ; Balanced ;
; Carry Chain Length -- Stratix/Stratix GX/Cyclone/MAX II/Cyclone II/Cyclone III ; 70 ; 70 ;
; Auto Carry Chains ; On ; On ;
; Auto Open-Drain Pins ; On ; On ;
; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
; Perform gate-level register retiming ; Off ; Off ;
; Allow register retiming to trade off Tsu/Tco with Fmax ; On ; On ;
; Auto ROM Replacement ; On ; On ;
; Auto RAM Replacement ; On ; On ;
; Auto Shift Register Replacement ; Auto ; Auto ;
; Auto Clock Enable Replacement ; On ; On ;
; Allow Synchronous Control Signals ; On ; On ;
; Force Use of Synchronous Clear Signals ; Off ; Off ;
; Auto RAM to Logic Cell Conversion ; Off ; Off ;
; Auto Resource Sharing ; Off ; Off ;
; Allow Any RAM Size For Recognition ; Off ; Off ;
; Allow Any ROM Size For Recognition ; Off ; Off ;
; Allow Any Shift Register Size For Recognition ; Off ; Off ;
; Ignore translate_off and synthesis_off directives ; Off ; Off ;
; Show Parameter Settings Tables in Synthesis Report ; On ; On ;
; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
; Retiming Meta-Stability Register Sequence Length ; 2 ; 2 ;
; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ;
; HDL message level ; Level2 ; Level2 ;
; Suppress Register Optimization Related Messages ; Off ; Off ;
; Number of Removed Registers Reported in Synthesis Report ; 100 ; 100 ;
; Clock MUX Protection ; On ; On ;
; Block Design Naming ; Auto ; Auto ;
+--------------------------------------------------------------------------------+--------------------+--------------------+
+---------------------------------+
; Analysis & Elaboration Messages ;
+---------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Elaboration
Info: Version 7.2 Build 207 03/18/2008 Service Pack 3 SJ Full Version
Info: Processing started: Mon Jul 14 19:37:17 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off Time -c Time --analysis_and_elaboration
Info: Found 5 design units, including 5 entities, in source file Time.v
Info: Found entity 1: Time
Info: Found entity 2: DecDis
Info: Found entity 3: SecClkGen
Info: Found entity 4: MinClkGen
Info: Found entity 5: HouClkGen
Info: Elaborating entity "Time" for the top level hierarchy
Warning (10034): Output port "LEDG[8]" at Time.v(9) has no driver
Warning (10034): Output port "LEDG[7]" at Time.v(9) has no driver
Warning (10034): Output port "LEDG[6]" at Time.v(9) has no driver
Warning (10034): Output port "LEDG[5]" at Time.v(9) has no driver
Warning (10034): Output port "LEDG[4]" at Time.v(9) has no driver
Warning (10034): Output port "LEDG[3]" at Time.v(9) has no driver
Warning (10034): Output port "LEDG[2]" at Time.v(9) has no driver
Warning (10034): Output port "LEDG[1]" at Time.v(9) has no driver
Warning (10034): Output port "LEDG[0]" at Time.v(9) has no driver
Info: Elaborating entity "SecClkGen" for hierarchy "SecClkGen:SCG1"
Warning (10230): Verilog HDL assignment warning at Time.v(83): truncated value with size 6 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at Time.v(84): truncated value with size 6 to match size of target (4)
Info: Elaborating entity "DecDis" for hierarchy "DecDis:SC1"
Info: Elaborating entity "MinClkGen" for hierarchy "MinClkGen:MCG1"
Warning (10230): Verilog HDL assignment warning at Time.v(110): truncated value with size 6 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at Time.v(111): truncated value with size 6 to match size of target (4)
Info: Elaborating entity "HouClkGen" for hierarchy "HouClkGen:HCG1"
Warning (10230): Verilog HDL assignment warning at Time.v(138): truncated value with size 5 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at Time.v(139): truncated value with size 5 to match size of target (4)
Info: Quartus II Analysis & Elaboration was successful. 0 errors, 15 warnings
Info: Allocated 137 megabytes of memory during processing
Info: Processing ended: Mon Jul 14 19:37:19 2008
Info: Elapsed time: 00:00:02
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