cursor.map.qmsg

ALTERA的DE2平台VGA接口应用

{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 Cursor.v(137) " "Warning (10230): Verilog HDL assignment warning at Cursor.v(137): truncated value with size 32 to match size of target (10)" {  } { { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 137 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 Cursor.v(154) " "Warning (10230): Verilog HDL assignment warning at Cursor.v(154): truncated value with size 32 to match size of target (10)" {  } { { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 154 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 Cursor.v(177) " "Warning (10230): Verilog HDL assignment warning at Cursor.v(177): truncated value with size 32 to match size of target (10)" {  } { { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 177 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "LEDG\[8\] Cursor.v(19) " "Warning (10034): Output port \"LEDG\[8\]\" at Cursor.v(19) has no driver" {  } { { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 19 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "LEDG\[7\] Cursor.v(19) " "Warning (10034): Output port \"LEDG\[7\]\" at Cursor.v(19) has no driver" {  } { { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 19 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "LEDG\[6\] Cursor.v(19) " "Warning (10034): Output port \"LEDG\[6\]\" at Cursor.v(19) has no driver" {  } { { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 19 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "LEDG\[5\] Cursor.v(19) " "Warning (10034): Output port \"LEDG\[5\]\" at Cursor.v(19) has no driver" {  } { { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 19 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "LEDG\[4\] Cursor.v(19) " "Warning (10034): Output port \"LEDG\[4\]\" at Cursor.v(19) has no driver" {  } { { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 19 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "" 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "B_Val\[1\] B_Val\[0\] " "Info: Duplicate register \"B_Val\[1\]\" merged to single register \"B_Val\[0\]\"" {  } { { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 63 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "B_Val\[2\] B_Val\[0\] " "Info: Duplicate register \"B_Val\[2\]\" merged to single register \"B_Val\[0\]\"" {  } { { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 63 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "B_Val\[3\] B_Val\[0\] " "Info: Duplicate register \"B_Val\[3\]\" merged to single register \"B_Val\[0\]\"" {  } { { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 63 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "B_Val\[4\] B_Val\[0\] " "Info: Duplicate register \"B_Val\[4\]\" merged to single register \"B_Val\[0\]\"" {  } { { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 63 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "B_Val\[5\] B_Val\[0\] " "Info: Duplicate register \"B_Val\[5\]\" merged to single register \"B_Val\[0\]\"" {  } { { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 63 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "B_Val\[6\] B_Val\[0\] " "Info: Duplicate register \"B_Val\[6\]\" merged to single register \"B_Val\[0\]\"" {  } { { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 63 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "B_Val\[7\] B_Val\[0\] " "Info: Duplicate register \"B_Val\[7\]\" merged to single register \"B_Val\[0\]\"" {  } { { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 63 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "B_Val\[8\] B_Val\[0\] " "Info: Duplicate register \"B_Val\[8\]\" merged to single register \"B_Val\[0\]\"" {  } { { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 63 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "B_Val\[9\] B_Val\[0\] " "Info: Duplicate register \"B_Val\[9\]\" merged to single register \"B_Val\[0\]\"" {  } { { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 63 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "G_Val\[0\] B_Val\[0\] " "Info: Duplicate register \"G_Val\[0\]\" merged to single register \"B_Val\[0\]\"" {  } { { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 63 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "G_Val\[1\] B_Val\[0\] " "Info: Duplicate register \"G_Val\[1\]\" merged to single register \"B_Val\[0\]\"" {  } { { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 63 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "G_Val\[2\] B_Val\[0\] " "Info: Duplicate register \"G_Val\[2\]\" merged to single register \"B_Val\[0\]\"" {  } { { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 63 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "G_Val\[3\] B_Val\[0\] " "Info: Duplicate register \"G_Val\[3\]\" merged to single register \"B_Val\[0\]\"" {  } { { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 63 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "G_Val\[4\] B_Val\[0\] " "Info: Duplicate register \"G_Val\[4\]\" merged to single register \"B_Val\[0\]\"" {  } { { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 63 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "G_Val\[5\] B_Val\[0\] " "Info: Duplicate register \"G_Val\[5\]\" merged to single register \"B_Val\[0\]\"" {  } { { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 63 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "G_Val\[6\] B_Val\[0\] " "Info: Duplicate register \"G_Val\[6\]\" merged to single register \"B_Val\[0\]\"" {  } { { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 63 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "G_Val\[7\] B_Val\[0\] " "Info: Duplicate register \"G_Val\[7\]\" merged to single register \"B_Val\[0\]\"" {  } { { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 63 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "G_Val\[8\] B_Val\[0\] " "Info: Duplicate register \"G_Val\[8\]\" merged to single register \"B_Val\[0\]\"" {  } { { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 63 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "G_Val\[9\] B_Val\[0\] " "Info: Duplicate register \"G_Val\[9\]\" merged to single register \"B_Val\[0\]\"" {  } { { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 63 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "R_Val\[0\] B_Val\[0\] " "Info: Duplicate register \"R_Val\[0\]\" merged to single register \"B_Val\[0\]\"" {  } { { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 63 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "R_Val\[1\] B_Val\[0\] " "Info: Duplicate register \"R_Val\[1\]\" merged to single register \"B_Val\[0\]\"" {  } { { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 63 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "R_Val\[2\] B_Val\[0\] " "Info: Duplicate register \"R_Val\[2\]\" merged to single register \"B_Val\[0\]\"" {  } { { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 63 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "R_Val\[3\] B_Val\[0\] " "Info: Duplicate register \"R_Val\[3\]\" merged to single register \"B_Val\[0\]\"" {  } { { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 63 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "R_Val\[4\] B_Val\[0\] " "Info: Duplicate register \"R_Val\[4\]\" merged to single register \"B_Val\[0\]\"" {  } { { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 63 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "R_Val\[5\] B_Val\[0\] " "Info: Duplicate register \"R_Val\[5\]\" merged to single register \"B_Val\[0\]\"" {  } { { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 63 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "R_Val\[6\] B_Val\[0\] " "Info: Duplicate register \"R_Val\[6\]\" merged to single register \"B_Val\[0\]\"" {  } { { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 63 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "R_Val\[7\] B_Val\[0\] " "Info: Duplicate register \"R_Val\[7\]\" merged to single register \"B_Val\[0\]\"" {  } { { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 63 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "R_Val\[8\] B_Val\[0\] " "Info: Duplicate register \"R_Val\[8\]\" merged to single register \"B_Val\[0\]\"" {  } { { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 63 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "R_Val\[9\] B_Val\[0\] " "Info: Duplicate register \"R_Val\[9\]\" merged to single register \"B_Val\[0\]\"" {  } { { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 63 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0 "" 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "LEDG\[4\] GND " "Warning (13410): Pin \"LEDG\[4\]\" stuck at GND" {  } { { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 19 -1 0 } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0} { "Warning" "WOPT_MLS_STUCK_PIN" "LEDG\[5\] GND " "Warning (13410): Pin \"LEDG\[5\]\" stuck at GND" {  } { { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 19 -1 0 } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0} { "Warning" "WOPT_MLS_STUCK_PIN" "LEDG\[6\] GND " "Warning (13410): Pin \"LEDG\[6\]\" stuck at GND" {  } { { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 19 -1 0 } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0} { "Warning" "WOPT_MLS_STUCK_PIN" "LEDG\[7\] GND " "Warning (13410): Pin \"LEDG\[7\]\" stuck at GND" {  } { { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 19 -1 0 } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0} { "Warning" "WOPT_MLS_STUCK_PIN" "LEDG\[8\] GND " "Warning (13410): Pin \"LEDG\[8\]\" stuck at GND" {  } { { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 19 -1 0 } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0} { "Warning" "WOPT_MLS_STUCK_PIN" "VGA_SYNC GND " "Warning (13410): Pin \"VGA_SYNC\" stuck at GND" {  } { { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 25 -1 0 } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0 "" 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/PROGRAMING/fpga/Cursor/Cursor.map.smsg " "Info: Generated suppressed messages file D:/PROGRAMING/fpga/Cursor/Cursor.map.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0}
{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "17 " "Warning: Design contains 17 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[0\] " "Warning (15610): No output dependent on input pin \"SW\[0\]\"" {  } { { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 15 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[1\] " "Warning (15610): No output dependent on input pin \"SW\[1\]\"" {  } { { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 15 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[2\] " "Warning (15610): No output dependent on input pin \"SW\[2\]\"" {  } { { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 15 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[3\] " "Warning (15610): No output dependent on input pin \"SW\[3\]\"" {  } { { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 15 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[4\] " "Warning (15610): No output dependent on input pin \"SW\[4\]\"" {  } { { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 15 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[5\] " "Warning (15610): No output dependent on input pin \"SW\[5\]\"" {  } { { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 15 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[6\] " "Warning (15610): No output dependent on input pin \"SW\[6\]\"" {  } { { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 15 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[7\] " "Warning (15610): No output dependent on input pin \"SW\[7\]\"" {  } { { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 15 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[8\] " "Warning (15610): No output dependent on input pin \"SW\[8\]\"" {  } { { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 15 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[9\] " "Warning (15610): No output dependent on input pin \"SW\[9\]\"" {  } { { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 15 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[10\] " "Warning (15610): No output dependent on input pin \"SW\[10\]\"" {  } { { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 15 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[11\] " "Warning (15610): No output dependent on input pin \"SW\[11\]\"" {  } { { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 15 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[12\] " "Warning (15610): No output dependent on input pin \"SW\[12\]\"" {  } { { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 15 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[13\] " "Warning (15610): No output dependent on input pin \"SW\[13\]\"" {  } { { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 15 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[14\] " "Warning (15610): No output dependent on input pin \"SW\[14\]\"" {  } { { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 15 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[15\] " "Warning (15610): No output dependent on input pin \"SW\[15\]\"" {  } { { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 15 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[16\] " "Warning (15610): No output dependent on input pin \"SW\[16\]\"" {  } { { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 15 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0}  } {  } 0 0 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "381 " "Info: Implemented 381 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "23 " "Info: Implemented 23 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "44 " "Info: Implemented 44 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_LCELLS" "314 " "Info: Implemented 314 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 42 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 42 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "144 " "Info: Allocated 144 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Wed Jul 16 17:25:02 2008 " "Info: Processing ended: Wed Jul 16 17:25:02 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}