cursor.map.qmsg

ALTERA的DE2平台VGA接口应用

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 207 03/18/2008 Service Pack 3 SJ Full Version " "Info: Version 7.2 Build 207 03/18/2008 Service Pack 3 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Jul 16 17:24:57 2008 " "Info: Processing started: Wed Jul 16 17:24:57 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off Cursor -c Cursor " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off Cursor -c Cursor" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "Cursor.v(79) " "Warning (10268): Verilog HDL information at Cursor.v(79): Always Construct contains both blocking and non-blocking assignments" {  } { { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 79 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: Always Construct contains both blocking and non-blocking assignments" 1 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Cursor.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file Cursor.v" { { "Info" "ISGN_ENTITY_NAME" "1 Cursor " "Info: Found entity 1: Cursor" {  } { { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "Cursor " "Info: Elaborating entity \"Cursor\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 26 Cursor.v(85) " "Warning (10230): Verilog HDL assignment warning at Cursor.v(85): truncated value with size 32 to match size of target (26)" {  } { { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 85 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 Cursor.v(90) " "Warning (10230): Verilog HDL assignment warning at Cursor.v(90): truncated value with size 32 to match size of target (10)" {  } { { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 90 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 26 Cursor.v(100) " "Warning (10230): Verilog HDL assignment warning at Cursor.v(100): truncated value with size 32 to match size of target (26)" {  } { { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 100 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 Cursor.v(105) " "Warning (10230): Verilog HDL assignment warning at Cursor.v(105): truncated value with size 32 to match size of target (10)" {  } { { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 105 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 Cursor.v(107) " "Warning (10230): Verilog HDL assignment warning at Cursor.v(107): truncated value with size 32 to match size of target (10)" {  } { { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 107 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 26 Cursor.v(115) " "Warning (10230): Verilog HDL assignment warning at Cursor.v(115): truncated value with size 32 to match size of target (26)" {  } { { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 115 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 Cursor.v(120) " "Warning (10230): Verilog HDL assignment warning at Cursor.v(120): truncated value with size 32 to match size of target (10)" {  } { { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 120 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 26 Cursor.v(130) " "Warning (10230): Verilog HDL assignment warning at Cursor.v(130): truncated value with size 32 to match size of target (26)" {  } { { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 130 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 Cursor.v(135) " "Warning (10230): Verilog HDL assignment warning at Cursor.v(135): truncated value with size 32 to match size of target (10)" {  } { { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 135 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}