cursor.tan.qmsg

ALTERA的DE2平台VGA接口应用

{ "Info" "ITDB_FULL_TCO_RESULT" "CLOCK_50 VGA_BLANK VGA_HS~reg0 10.483 ns register " "Info: tco from clock \"CLOCK_50\" to destination pin \"VGA_BLANK\" through register \"VGA_HS~reg0\" is 10.483 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK_50 source 2.679 ns + Longest register " "Info: + Longest clock path from clock \"CLOCK_50\" to source register is 2.679 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns CLOCK_50 1 CLK PIN_N2 2 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 2; CLK Node = 'CLOCK_50'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns CLOCK_50~clkctrl 2 COMB CLKCTRL_G2 151 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 151; COMB Node = 'CLOCK_50~clkctrl'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.118 ns" { CLOCK_50 CLOCK_50~clkctrl } "NODE_NAME" } } { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.025 ns) + CELL(0.537 ns) 2.679 ns VGA_HS~reg0 3 REG LCFF_X45_Y21_N29 2 " "Info: 3: + IC(1.025 ns) + CELL(0.537 ns) = 2.679 ns; Loc. = LCFF_X45_Y21_N29; Fanout = 2; REG Node = 'VGA_HS~reg0'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.562 ns" { CLOCK_50~clkctrl VGA_HS~reg0 } "NODE_NAME" } } { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 162 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.33 % ) " "Info: Total cell delay = 1.536 ns ( 57.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.143 ns ( 42.67 % ) " "Info: Total interconnect delay = 1.143 ns ( 42.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.679 ns" { CLOCK_50 CLOCK_50~clkctrl VGA_HS~reg0 } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.679 ns" { CLOCK_50 {} CLOCK_50~combout {} CLOCK_50~clkctrl {} VGA_HS~reg0 {} } { 0.000ns 0.000ns 0.118ns 1.025ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 162 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.554 ns + Longest register pin " "Info: + Longest register to pin delay is 7.554 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns VGA_HS~reg0 1 REG LCFF_X45_Y21_N29 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X45_Y21_N29; Fanout = 2; REG Node = 'VGA_HS~reg0'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { VGA_HS~reg0 } "NODE_NAME" } } { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 162 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.787 ns) + CELL(0.150 ns) 0.937 ns VGA_BLANK~0 2 COMB LCCOMB_X44_Y19_N4 1 " "Info: 2: + IC(0.787 ns) + CELL(0.150 ns) = 0.937 ns; Loc. = LCCOMB_X44_Y19_N4; Fanout = 1; COMB Node = 'VGA_BLANK~0'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.937 ns" { VGA_HS~reg0 VGA_BLANK~0 } "NODE_NAME" } } { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.819 ns) + CELL(2.798 ns) 7.554 ns VGA_BLANK 3 PIN PIN_D6 0 " "Info: 3: + IC(3.819 ns) + CELL(2.798 ns) = 7.554 ns; Loc. = PIN_D6; Fanout = 0; PIN Node = 'VGA_BLANK'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.617 ns" { VGA_BLANK~0 VGA_BLANK } "NODE_NAME" } } { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.948 ns ( 39.03 % ) " "Info: Total cell delay = 2.948 ns ( 39.03 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.606 ns ( 60.97 % ) " "Info: Total interconnect delay = 4.606 ns ( 60.97 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.554 ns" { VGA_HS~reg0 VGA_BLANK~0 VGA_BLANK } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.554 ns" { VGA_HS~reg0 {} VGA_BLANK~0 {} VGA_BLANK {} } { 0.000ns 0.787ns 3.819ns } { 0.000ns 0.150ns 2.798ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.679 ns" { CLOCK_50 CLOCK_50~clkctrl VGA_HS~reg0 } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.679 ns" { CLOCK_50 {} CLOCK_50~combout {} CLOCK_50~clkctrl {} VGA_HS~reg0 {} } { 0.000ns 0.000ns 0.118ns 1.025ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.554 ns" { VGA_HS~reg0 VGA_BLANK~0 VGA_BLANK } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.554 ns" { VGA_HS~reg0 {} VGA_BLANK~0 {} VGA_BLANK {} } { 0.000ns 0.787ns 3.819ns } { 0.000ns 0.150ns 2.798ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "CLOCK_50 VGA_CLK 5.541 ns Longest " "Info: Longest tpd from source pin \"CLOCK_50\" to destination pin \"VGA_CLK\" is 5.541 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns CLOCK_50 1 CLK PIN_N2 2 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 2; CLK Node = 'CLOCK_50'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.744 ns) + CELL(2.798 ns) 5.541 ns VGA_CLK 2 PIN PIN_B8 0 " "Info: 2: + IC(1.744 ns) + CELL(2.798 ns) = 5.541 ns; Loc. = PIN_B8; Fanout = 0; PIN Node = 'VGA_CLK'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.542 ns" { CLOCK_50 VGA_CLK } "NODE_NAME" } } { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.797 ns ( 68.53 % ) " "Info: Total cell delay = 3.797 ns ( 68.53 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.744 ns ( 31.47 % ) " "Info: Total interconnect delay = 1.744 ns ( 31.47 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.541 ns" { CLOCK_50 VGA_CLK } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.541 ns" { CLOCK_50 {} CLOCK_50~combout {} VGA_CLK {} } { 0.000ns 0.000ns 1.744ns } { 0.000ns 0.999ns 2.798ns } "" } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "LEDG\[1\]~reg0 KEY\[1\] CLOCK_50 -3.127 ns register " "Info: th for register \"LEDG\[1\]~reg0\" (data pin = \"KEY\[1\]\", clock pin = \"CLOCK_50\") is -3.127 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK_50 destination 2.689 ns + Longest register " "Info: + Longest clock path from clock \"CLOCK_50\" to destination register is 2.689 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns CLOCK_50 1 CLK PIN_N2 2 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 2; CLK Node = 'CLOCK_50'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns CLOCK_50~clkctrl 2 COMB CLKCTRL_G2 151 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 151; COMB Node = 'CLOCK_50~clkctrl'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.118 ns" { CLOCK_50 CLOCK_50~clkctrl } "NODE_NAME" } } { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.035 ns) + CELL(0.537 ns) 2.689 ns LEDG\[1\]~reg0 3 REG LCFF_X60_Y19_N17 2 " "Info: 3: + IC(1.035 ns) + CELL(0.537 ns) = 2.689 ns; Loc. = LCFF_X60_Y19_N17; Fanout = 2; REG Node = 'LEDG\[1\]~reg0'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.572 ns" { CLOCK_50~clkctrl LEDG[1]~reg0 } "NODE_NAME" } } { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 79 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.12 % ) " "Info: Total cell delay = 1.536 ns ( 57.12 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.153 ns ( 42.88 % ) " "Info: Total interconnect delay = 1.153 ns ( 42.88 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.689 ns" { CLOCK_50 CLOCK_50~clkctrl LEDG[1]~reg0 } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.689 ns" { CLOCK_50 {} CLOCK_50~combout {} CLOCK_50~clkctrl {} LEDG[1]~reg0 {} } { 0.000ns 0.000ns 0.118ns 1.035ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.266 ns + " "Info: + Micro hold delay of destination is 0.266 ns" {  } { { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 79 0 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.082 ns - Shortest pin register " "Info: - Shortest pin to register delay is 6.082 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.842 ns) 0.842 ns KEY\[1\] 1 PIN PIN_N23 7 " "Info: 1: + IC(0.000 ns) + CELL(0.842 ns) = 0.842 ns; Loc. = PIN_N23; Fanout = 7; PIN Node = 'KEY\[1\]'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { KEY[1] } "NODE_NAME" } } { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.006 ns) + CELL(0.150 ns) 5.998 ns LEDG~216 2 COMB LCCOMB_X60_Y19_N16 1 " "Info: 2: + IC(5.006 ns) + CELL(0.150 ns) = 5.998 ns; Loc. = LCCOMB_X60_Y19_N16; Fanout = 1; COMB Node = 'LEDG~216'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.156 ns" { KEY[1] LEDG~216 } "NODE_NAME" } } { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 6.082 ns LEDG\[1\]~reg0 3 REG LCFF_X60_Y19_N17 2 " "Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 6.082 ns; Loc. = LCFF_X60_Y19_N17; Fanout = 2; REG Node = 'LEDG\[1\]~reg0'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.084 ns" { LEDG~216 LEDG[1]~reg0 } "NODE_NAME" } } { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 79 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.076 ns ( 17.69 % ) " "Info: Total cell delay = 1.076 ns ( 17.69 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.006 ns ( 82.31 % ) " "Info: Total interconnect delay = 5.006 ns ( 82.31 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.082 ns" { KEY[1] LEDG~216 LEDG[1]~reg0 } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.082 ns" { KEY[1] {} KEY[1]~combout {} LEDG~216 {} LEDG[1]~reg0 {} } { 0.000ns 0.000ns 5.006ns 0.000ns } { 0.000ns 0.842ns 0.150ns 0.084ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.689 ns" { CLOCK_50 CLOCK_50~clkctrl LEDG[1]~reg0 } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.689 ns" { CLOCK_50 {} CLOCK_50~combout {} CLOCK_50~clkctrl {} LEDG[1]~reg0 {} } { 0.000ns 0.000ns 0.118ns 1.035ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.082 ns" { KEY[1] LEDG~216 LEDG[1]~reg0 } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.082 ns" { KEY[1] {} KEY[1]~combout {} LEDG~216 {} LEDG[1]~reg0 {} } { 0.000ns 0.000ns 5.006ns 0.000ns } { 0.000ns 0.842ns 0.150ns 0.084ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}