cursor.tan.qmsg

ALTERA的DE2平台VGA接口应用

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "CLOCK_50 " "Info: Assuming node \"CLOCK_50\" is an undefined clock" {  } { { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 16 -1 0 } } { "e:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLOCK_50" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLOCK_50 register Y\[0\] register B_Val\[0\] 165.73 MHz 6.034 ns Internal " "Info: Clock \"CLOCK_50\" has Internal fmax of 165.73 MHz between source register \"Y\[0\]\" and destination register \"B_Val\[0\]\" (period= 6.034 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.815 ns + Longest register register " "Info: + Longest register to register delay is 5.815 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Y\[0\] 1 REG LCFF_X46_Y18_N27 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X46_Y18_N27; Fanout = 5; REG Node = 'Y\[0\]'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { Y[0] } "NODE_NAME" } } { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 79 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.321 ns) + CELL(0.393 ns) 0.714 ns Add2~133 2 COMB LCCOMB_X46_Y18_N0 2 " "Info: 2: + IC(0.321 ns) + CELL(0.393 ns) = 0.714 ns; Loc. = LCCOMB_X46_Y18_N0; Fanout = 2; COMB Node = 'Add2~133'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.714 ns" { Y[0] Add2~133 } "NODE_NAME" } } { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 65 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 0.785 ns Add2~135 3 COMB LCCOMB_X46_Y18_N2 2 " "Info: 3: + IC(0.000 ns) + CELL(0.071 ns) = 0.785 ns; Loc. = LCCOMB_X46_Y18_N2; Fanout = 2; COMB Node = 'Add2~135'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { Add2~133 Add2~135 } "NODE_NAME" } } { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 65 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 0.856 ns Add2~137 4 COMB LCCOMB_X46_Y18_N4 2 " "Info: 4: + IC(0.000 ns) + CELL(0.071 ns) = 0.856 ns; Loc. = LCCOMB_X46_Y18_N4; Fanout = 2; COMB Node = 'Add2~137'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { Add2~135 Add2~137 } "NODE_NAME" } } { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 65 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 0.927 ns Add2~139 5 COMB LCCOMB_X46_Y18_N6 2 " "Info: 5: + IC(0.000 ns) + CELL(0.071 ns) = 0.927 ns; Loc. = LCCOMB_X46_Y18_N6; Fanout = 2; COMB Node = 'Add2~139'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { Add2~137 Add2~139 } "NODE_NAME" } } { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 65 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 0.998 ns Add2~141 6 COMB LCCOMB_X46_Y18_N8 2 " "Info: 6: + IC(0.000 ns) + CELL(0.071 ns) = 0.998 ns; Loc. = LCCOMB_X46_Y18_N8; Fanout = 2; COMB Node = 'Add2~141'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { Add2~139 Add2~141 } "NODE_NAME" } } { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 65 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.410 ns) 1.408 ns Add2~142 7 COMB LCCOMB_X46_Y18_N10 3 " "Info: 7: + IC(0.000 ns) + CELL(0.410 ns) = 1.408 ns; Loc. = LCCOMB_X46_Y18_N10; Fanout = 3; COMB Node = 'Add2~142'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.410 ns" { Add2~141 Add2~142 } "NODE_NAME" } } { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 65 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.739 ns) + CELL(0.414 ns) 2.561 ns Add3~99 8 COMB LCCOMB_X46_Y19_N10 2 " "Info: 8: + IC(0.739 ns) + CELL(0.414 ns) = 2.561 ns; Loc. = LCCOMB_X46_Y19_N10; Fanout = 2; COMB Node = 'Add3~99'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.153 ns" { Add2~142 Add3~99 } "NODE_NAME" } } { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 65 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 2.632 ns Add3~101 9 COMB LCCOMB_X46_Y19_N12 2 " "Info: 9: + IC(0.000 ns) + CELL(0.071 ns) = 2.632 ns; Loc. = LCCOMB_X46_Y19_N12; Fanout = 2; COMB Node = 'Add3~101'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { Add3~99 Add3~101 } "NODE_NAME" } } { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 65 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.159 ns) 2.791 ns Add3~103 10 COMB LCCOMB_X46_Y19_N14 2 " "Info: 10: + IC(0.000 ns) + CELL(0.159 ns) = 2.791 ns; Loc. = LCCOMB_X46_Y19_N14; Fanout = 2; COMB Node = 'Add3~103'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.159 ns" { Add3~101 Add3~103 } "NODE_NAME" } } { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 65 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.410 ns) 3.201 ns Add3~104 11 COMB LCCOMB_X46_Y19_N16 1 " "Info: 11: + IC(0.000 ns) + CELL(0.410 ns) = 3.201 ns; Loc. = LCCOMB_X46_Y19_N16; Fanout = 1; COMB Node = 'Add3~104'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.410 ns" { Add3~103 Add3~104 } "NODE_NAME" } } { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 65 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.449 ns) + CELL(0.414 ns) 4.064 ns LessThan3~174 12 COMB LCCOMB_X45_Y19_N26 1 " "Info: 12: + IC(0.449 ns) + CELL(0.414 ns) = 4.064 ns; Loc. = LCCOMB_X45_Y19_N26; Fanout = 1; COMB Node = 'LessThan3~174'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.863 ns" { Add3~104 LessThan3~174 } "NODE_NAME" } } { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 65 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.410 ns) 4.474 ns LessThan3~175 13 COMB LCCOMB_X45_Y19_N28 1 " "Info: 13: + IC(0.000 ns) + CELL(0.410 ns) = 4.474 ns; Loc. = LCCOMB_X45_Y19_N28; Fanout = 1; COMB Node = 'LessThan3~175'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.410 ns" { LessThan3~174 LessThan3~175 } "NODE_NAME" } } { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 65 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.716 ns) + CELL(0.150 ns) 5.340 ns always0~42 14 COMB LCCOMB_X46_Y21_N0 1 " "Info: 14: + IC(0.716 ns) + CELL(0.150 ns) = 5.340 ns; Loc. = LCCOMB_X46_Y21_N0; Fanout = 1; COMB Node = 'always0~42'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.866 ns" { LessThan3~175 always0~42 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.241 ns) + CELL(0.150 ns) 5.731 ns always0~44 15 COMB LCCOMB_X46_Y21_N20 1 " "Info: 15: + IC(0.241 ns) + CELL(0.150 ns) = 5.731 ns; Loc. = LCCOMB_X46_Y21_N20; Fanout = 1; COMB Node = 'always0~44'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.391 ns" { always0~42 always0~44 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 5.815 ns B_Val\[0\] 16 REG LCFF_X46_Y21_N21 30 " "Info: 16: + IC(0.000 ns) + CELL(0.084 ns) = 5.815 ns; Loc. = LCFF_X46_Y21_N21; Fanout = 30; REG Node = 'B_Val\[0\]'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.084 ns" { always0~44 B_Val[0] } "NODE_NAME" } } { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 63 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.349 ns ( 57.59 % ) " "Info: Total cell delay = 3.349 ns ( 57.59 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.466 ns ( 42.41 % ) " "Info: Total interconnect delay = 2.466 ns ( 42.41 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.815 ns" { Y[0] Add2~133 Add2~135 Add2~137 Add2~139 Add2~141 Add2~142 Add3~99 Add3~101 Add3~103 Add3~104 LessThan3~174 LessThan3~175 always0~42 always0~44 B_Val[0] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.815 ns" { Y[0] {} Add2~133 {} Add2~135 {} Add2~137 {} Add2~139 {} Add2~141 {} Add2~142 {} Add3~99 {} Add3~101 {} Add3~103 {} Add3~104 {} LessThan3~174 {} LessThan3~175 {} always0~42 {} always0~44 {} B_Val[0] {} } { 0.000ns 0.321ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.739ns 0.000ns 0.000ns 0.000ns 0.449ns 0.000ns 0.716ns 0.241ns 0.000ns } { 0.000ns 0.393ns 0.071ns 0.071ns 0.071ns 0.071ns 0.410ns 0.414ns 0.071ns 0.159ns 0.410ns 0.414ns 0.410ns 0.150ns 0.150ns 0.084ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.005 ns - Smallest " "Info: - Smallest clock skew is -0.005 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK_50 destination 2.679 ns + Shortest register " "Info: + Shortest clock path from clock \"CLOCK_50\" to destination register is 2.679 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns CLOCK_50 1 CLK PIN_N2 2 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 2; CLK Node = 'CLOCK_50'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns CLOCK_50~clkctrl 2 COMB CLKCTRL_G2 151 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 151; COMB Node = 'CLOCK_50~clkctrl'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.118 ns" { CLOCK_50 CLOCK_50~clkctrl } "NODE_NAME" } } { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.025 ns) + CELL(0.537 ns) 2.679 ns B_Val\[0\] 3 REG LCFF_X46_Y21_N21 30 " "Info: 3: + IC(1.025 ns) + CELL(0.537 ns) = 2.679 ns; Loc. = LCFF_X46_Y21_N21; Fanout = 30; REG Node = 'B_Val\[0\]'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.562 ns" { CLOCK_50~clkctrl B_Val[0] } "NODE_NAME" } } { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 63 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.33 % ) " "Info: Total cell delay = 1.536 ns ( 57.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.143 ns ( 42.67 % ) " "Info: Total interconnect delay = 1.143 ns ( 42.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.679 ns" { CLOCK_50 CLOCK_50~clkctrl B_Val[0] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.679 ns" { CLOCK_50 {} CLOCK_50~combout {} CLOCK_50~clkctrl {} B_Val[0] {} } { 0.000ns 0.000ns 0.118ns 1.025ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK_50 source 2.684 ns - Longest register " "Info: - Longest clock path from clock \"CLOCK_50\" to source register is 2.684 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns CLOCK_50 1 CLK PIN_N2 2 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 2; CLK Node = 'CLOCK_50'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns CLOCK_50~clkctrl 2 COMB CLKCTRL_G2 151 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 151; COMB Node = 'CLOCK_50~clkctrl'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.118 ns" { CLOCK_50 CLOCK_50~clkctrl } "NODE_NAME" } } { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.030 ns) + CELL(0.537 ns) 2.684 ns Y\[0\] 3 REG LCFF_X46_Y18_N27 5 " "Info: 3: + IC(1.030 ns) + CELL(0.537 ns) = 2.684 ns; Loc. = LCFF_X46_Y18_N27; Fanout = 5; REG Node = 'Y\[0\]'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.567 ns" { CLOCK_50~clkctrl Y[0] } "NODE_NAME" } } { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 79 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.23 % ) " "Info: Total cell delay = 1.536 ns ( 57.23 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.148 ns ( 42.77 % ) " "Info: Total interconnect delay = 1.148 ns ( 42.77 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.684 ns" { CLOCK_50 CLOCK_50~clkctrl Y[0] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.684 ns" { CLOCK_50 {} CLOCK_50~combout {} CLOCK_50~clkctrl {} Y[0] {} } { 0.000ns 0.000ns 0.118ns 1.030ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.679 ns" { CLOCK_50 CLOCK_50~clkctrl B_Val[0] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.679 ns" { CLOCK_50 {} CLOCK_50~combout {} CLOCK_50~clkctrl {} B_Val[0] {} } { 0.000ns 0.000ns 0.118ns 1.025ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.684 ns" { CLOCK_50 CLOCK_50~clkctrl Y[0] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.684 ns" { CLOCK_50 {} CLOCK_50~combout {} CLOCK_50~clkctrl {} Y[0] {} } { 0.000ns 0.000ns 0.118ns 1.030ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 79 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 63 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.815 ns" { Y[0] Add2~133 Add2~135 Add2~137 Add2~139 Add2~141 Add2~142 Add3~99 Add3~101 Add3~103 Add3~104 LessThan3~174 LessThan3~175 always0~42 always0~44 B_Val[0] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.815 ns" { Y[0] {} Add2~133 {} Add2~135 {} Add2~137 {} Add2~139 {} Add2~141 {} Add2~142 {} Add3~99 {} Add3~101 {} Add3~103 {} Add3~104 {} LessThan3~174 {} LessThan3~175 {} always0~42 {} always0~44 {} B_Val[0] {} } { 0.000ns 0.321ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.739ns 0.000ns 0.000ns 0.000ns 0.449ns 0.000ns 0.716ns 0.241ns 0.000ns } { 0.000ns 0.393ns 0.071ns 0.071ns 0.071ns 0.071ns 0.410ns 0.414ns 0.071ns 0.159ns 0.410ns 0.414ns 0.410ns 0.150ns 0.150ns 0.084ns } "" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.679 ns" { CLOCK_50 CLOCK_50~clkctrl B_Val[0] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.679 ns" { CLOCK_50 {} CLOCK_50~combout {} CLOCK_50~clkctrl {} B_Val[0] {} } { 0.000ns 0.000ns 0.118ns 1.025ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.684 ns" { CLOCK_50 CLOCK_50~clkctrl Y[0] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.684 ns" { CLOCK_50 {} CLOCK_50~combout {} CLOCK_50~clkctrl {} Y[0] {} } { 0.000ns 0.000ns 0.118ns 1.030ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "X\[5\] KEY\[0\] CLOCK_50 7.015 ns register " "Info: tsu for register \"X\[5\]\" (data pin = \"KEY\[0\]\", clock pin = \"CLOCK_50\") is 7.015 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.733 ns + Longest pin register " "Info: + Longest pin to register delay is 9.733 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.862 ns) 0.862 ns KEY\[0\] 1 PIN PIN_G26 57 " "Info: 1: + IC(0.000 ns) + CELL(0.862 ns) = 0.862 ns; Loc. = PIN_G26; Fanout = 57; PIN Node = 'KEY\[0\]'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { KEY[0] } "NODE_NAME" } } { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.849 ns) + CELL(0.438 ns) 7.149 ns X\[0\]~1186 2 COMB LCCOMB_X48_Y21_N28 2 " "Info: 2: + IC(5.849 ns) + CELL(0.438 ns) = 7.149 ns; Loc. = LCCOMB_X48_Y21_N28; Fanout = 2; COMB Node = 'X\[0\]~1186'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.287 ns" { KEY[0] X[0]~1186 } "NODE_NAME" } } { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 79 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.246 ns) + CELL(0.150 ns) 7.545 ns X\[0\]~1188 3 COMB LCCOMB_X48_Y21_N26 1 " "Info: 3: + IC(0.246 ns) + CELL(0.150 ns) = 7.545 ns; Loc. = LCCOMB_X48_Y21_N26; Fanout = 1; COMB Node = 'X\[0\]~1188'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.396 ns" { X[0]~1186 X[0]~1188 } "NODE_NAME" } } { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 79 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.438 ns) + CELL(0.275 ns) 8.258 ns X\[0\]~1189 4 COMB LCCOMB_X48_Y21_N24 10 " "Info: 4: + IC(0.438 ns) + CELL(0.275 ns) = 8.258 ns; Loc. = LCCOMB_X48_Y21_N24; Fanout = 10; COMB Node = 'X\[0\]~1189'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.713 ns" { X[0]~1188 X[0]~1189 } "NODE_NAME" } } { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 79 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.971 ns) + CELL(0.420 ns) 9.649 ns Add5~1122 5 COMB LCCOMB_X47_Y20_N24 1 " "Info: 5: + IC(0.971 ns) + CELL(0.420 ns) = 9.649 ns; Loc. = LCCOMB_X47_Y20_N24; Fanout = 1; COMB Node = 'Add5~1122'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.391 ns" { X[0]~1189 Add5~1122 } "NODE_NAME" } } { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 90 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 9.733 ns X\[5\] 6 REG LCFF_X47_Y20_N25 6 " "Info: 6: + IC(0.000 ns) + CELL(0.084 ns) = 9.733 ns; Loc. = LCFF_X47_Y20_N25; Fanout = 6; REG Node = 'X\[5\]'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.084 ns" { Add5~1122 X[5] } "NODE_NAME" } } { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 79 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.229 ns ( 22.90 % ) " "Info: Total cell delay = 2.229 ns ( 22.90 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.504 ns ( 77.10 % ) " "Info: Total interconnect delay = 7.504 ns ( 77.10 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "9.733 ns" { KEY[0] X[0]~1186 X[0]~1188 X[0]~1189 Add5~1122 X[5] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "9.733 ns" { KEY[0] {} KEY[0]~combout {} X[0]~1186 {} X[0]~1188 {} X[0]~1189 {} Add5~1122 {} X[5] {} } { 0.000ns 0.000ns 5.849ns 0.246ns 0.438ns 0.971ns 0.000ns } { 0.000ns 0.862ns 0.438ns 0.150ns 0.275ns 0.420ns 0.084ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 79 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK_50 destination 2.682 ns - Shortest register " "Info: - Shortest clock path from clock \"CLOCK_50\" to destination register is 2.682 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns CLOCK_50 1 CLK PIN_N2 2 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 2; CLK Node = 'CLOCK_50'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns CLOCK_50~clkctrl 2 COMB CLKCTRL_G2 151 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 151; COMB Node = 'CLOCK_50~clkctrl'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.118 ns" { CLOCK_50 CLOCK_50~clkctrl } "NODE_NAME" } } { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.028 ns) + CELL(0.537 ns) 2.682 ns X\[5\] 3 REG LCFF_X47_Y20_N25 6 " "Info: 3: + IC(1.028 ns) + CELL(0.537 ns) = 2.682 ns; Loc. = LCFF_X47_Y20_N25; Fanout = 6; REG Node = 'X\[5\]'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.565 ns" { CLOCK_50~clkctrl X[5] } "NODE_NAME" } } { "Cursor.v" "" { Text "D:/PROGRAMING/fpga/Cursor/Cursor.v" 79 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.27 % ) " "Info: Total cell delay = 1.536 ns ( 57.27 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.146 ns ( 42.73 % ) " "Info: Total interconnect delay = 1.146 ns ( 42.73 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.682 ns" { CLOCK_50 CLOCK_50~clkctrl X[5] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.682 ns" { CLOCK_50 {} CLOCK_50~combout {} CLOCK_50~clkctrl {} X[5] {} } { 0.000ns 0.000ns 0.118ns 1.028ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "9.733 ns" { KEY[0] X[0]~1186 X[0]~1188 X[0]~1189 Add5~1122 X[5] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "9.733 ns" { KEY[0] {} KEY[0]~combout {} X[0]~1186 {} X[0]~1188 {} X[0]~1189 {} Add5~1122 {} X[5] {} } { 0.000ns 0.000ns 5.849ns 0.246ns 0.438ns 0.971ns 0.000ns } { 0.000ns 0.862ns 0.438ns 0.150ns 0.275ns 0.420ns 0.084ns } "" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.682 ns" { CLOCK_50 CLOCK_50~clkctrl X[5] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.682 ns" { CLOCK_50 {} CLOCK_50~combout {} CLOCK_50~clkctrl {} X[5] {} } { 0.000ns 0.000ns 0.118ns 1.028ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}