cursor.map.rpt

ALTERA的DE2平台VGA接口应用

+---------------------------------------------------------------+
; Registers Removed During Synthesis                            ;
+----------------------------------------+----------------------+
; Register name                          ; Reason for Removal   ;
+----------------------------------------+----------------------+
; B_Val[1..9]                            ; Merged with B_Val[0] ;
; G_Val[0..9]                            ; Merged with B_Val[0] ;
; R_Val[0..9]                            ; Merged with B_Val[0] ;
; Total Number of Removed Registers = 29 ;                      ;
+----------------------------------------+----------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 151   ;
; Number of registers using Synchronous Clear  ; 114   ;
; Number of registers using Synchronous Load   ; 2     ;
; Number of registers using Asynchronous Clear ; 22    ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 136   ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------------------------+
; Inverted Register Statistics                     ;
+----------------------------------------+---------+
; Inverted Register                      ; Fan out ;
+----------------------------------------+---------+
; X[6]                                   ; 3       ;
; X[5]                                   ; 4       ;
; X[2]                                   ; 3       ;
; Y[6]                                   ; 4       ;
; Y[5]                                   ; 4       ;
; Y[2]                                   ; 4       ;
; Total number of inverted registers = 6 ;         ;
+----------------------------------------+---------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                           ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 7:1                ; 7 bits    ; 28 LEs        ; 14 LEs               ; 14 LEs                 ; Yes        ; |Cursor|Y[9]               ;
; 7:1                ; 7 bits    ; 28 LEs        ; 14 LEs               ; 14 LEs                 ; Yes        ; |Cursor|X[0]               ;
; 7:1                ; 3 bits    ; 12 LEs        ; 6 LEs                ; 6 LEs                  ; Yes        ; |Cursor|Y[6]               ;
; 7:1                ; 3 bits    ; 12 LEs        ; 6 LEs                ; 6 LEs                  ; Yes        ; |Cursor|X[2]               ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+


+------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: Top-level Entity: |Cursor ;
+----------------+-------+-----------------------------------------------+
; Parameter Name ; Value ; Type                                          ;
+----------------+-------+-----------------------------------------------+
; CycH           ; 120   ; Signed Integer                                ;
; TotalH         ; 1040  ; Signed Integer                                ;
; FrontH         ; 181   ; Signed Integer                                ;
; BackH          ; 53    ; Signed Integer                                ;
; LengthX        ; 806   ; Signed Integer                                ;
; CycV           ; 6     ; Signed Integer                                ;
; TotalV         ; 666   ; Signed Integer                                ;
; FrontV         ; 27    ; Signed Integer                                ;
; BackV          ; 35    ; Signed Integer                                ;
; LengthY        ; 604   ; Signed Integer                                ;
; Wide           ; 16    ; Signed Integer                                ;
+----------------+-------+-----------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.2 Build 207 03/18/2008 Service Pack 3 SJ Full Version
    Info: Processing started: Wed Jul 16 17:24:57 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off Cursor -c Cursor
Info: Found 1 design units, including 1 entities, in source file Cursor.v
    Info: Found entity 1: Cursor
Info: Elaborating entity "Cursor" for the top level hierarchy
Warning (10230): Verilog HDL assignment warning at Cursor.v(85): truncated value with size 32 to match size of target (26)
Warning (10230): Verilog HDL assignment warning at Cursor.v(90): truncated value with size 32 to match size of target (10)
Warning (10230): Verilog HDL assignment warning at Cursor.v(100): truncated value with size 32 to match size of target (26)
Warning (10230): Verilog HDL assignment warning at Cursor.v(105): truncated value with size 32 to match size of target (10)
Warning (10230): Verilog HDL assignment warning at Cursor.v(107): truncated value with size 32 to match size of target (10)
Warning (10230): Verilog HDL assignment warning at Cursor.v(115): truncated value with size 32 to match size of target (26)
Warning (10230): Verilog HDL assignment warning at Cursor.v(120): truncated value with size 32 to match size of target (10)
Warning (10230): Verilog HDL assignment warning at Cursor.v(130): truncated value with size 32 to match size of target (26)
Warning (10230): Verilog HDL assignment warning at Cursor.v(135): truncated value with size 32 to match size of target (10)
Warning (10230): Verilog HDL assignment warning at Cursor.v(137): truncated value with size 32 to match size of target (10)
Warning (10230): Verilog HDL assignment warning at Cursor.v(154): truncated value with size 32 to match size of target (10)
Warning (10230): Verilog HDL assignment warning at Cursor.v(177): truncated value with size 32 to match size of target (10)
Warning (10034): Output port "LEDG[8]" at Cursor.v(19) has no driver
Warning (10034): Output port "LEDG[7]" at Cursor.v(19) has no driver
Warning (10034): Output port "LEDG[6]" at Cursor.v(19) has no driver
Warning (10034): Output port "LEDG[5]" at Cursor.v(19) has no driver
Warning (10034): Output port "LEDG[4]" at Cursor.v(19) has no driver
Info: Duplicate registers merged to single register
    Info: Duplicate register "B_Val[1]" merged to single register "B_Val[0]"
    Info: Duplicate register "B_Val[2]" merged to single register "B_Val[0]"
    Info: Duplicate register "B_Val[3]" merged to single register "B_Val[0]"
    Info: Duplicate register "B_Val[4]" merged to single register "B_Val[0]"
    Info: Duplicate register "B_Val[5]" merged to single register "B_Val[0]"
    Info: Duplicate register "B_Val[6]" merged to single register "B_Val[0]"
    Info: Duplicate register "B_Val[7]" merged to single register "B_Val[0]"
    Info: Duplicate register "B_Val[8]" merged to single register "B_Val[0]"
    Info: Duplicate register "B_Val[9]" merged to single register "B_Val[0]"
    Info: Duplicate register "G_Val[0]" merged to single register "B_Val[0]"
    Info: Duplicate register "G_Val[1]" merged to single register "B_Val[0]"
    Info: Duplicate register "G_Val[2]" merged to single register "B_Val[0]"
    Info: Duplicate register "G_Val[3]" merged to single register "B_Val[0]"
    Info: Duplicate register "G_Val[4]" merged to single register "B_Val[0]"
    Info: Duplicate register "G_Val[5]" merged to single register "B_Val[0]"
    Info: Duplicate register "G_Val[6]" merged to single register "B_Val[0]"
    Info: Duplicate register "G_Val[7]" merged to single register "B_Val[0]"
    Info: Duplicate register "G_Val[8]" merged to single register "B_Val[0]"
    Info: Duplicate register "G_Val[9]" merged to single register "B_Val[0]"
    Info: Duplicate register "R_Val[0]" merged to single register "B_Val[0]"
    Info: Duplicate register "R_Val[1]" merged to single register "B_Val[0]"
    Info: Duplicate register "R_Val[2]" merged to single register "B_Val[0]"
    Info: Duplicate register "R_Val[3]" merged to single register "B_Val[0]"
    Info: Duplicate register "R_Val[4]" merged to single register "B_Val[0]"
    Info: Duplicate register "R_Val[5]" merged to single register "B_Val[0]"
    Info: Duplicate register "R_Val[6]" merged to single register "B_Val[0]"
    Info: Duplicate register "R_Val[7]" merged to single register "B_Val[0]"
    Info: Duplicate register "R_Val[8]" merged to single register "B_Val[0]"
    Info: Duplicate register "R_Val[9]" merged to single register "B_Val[0]"
Warning: Output pins are stuck at VCC or GND
    Warning (13410): Pin "LEDG[4]" stuck at GND
    Warning (13410): Pin "LEDG[5]" stuck at GND
    Warning (13410): Pin "LEDG[6]" stuck at GND
    Warning (13410): Pin "LEDG[7]" stuck at GND
    Warning (13410): Pin "LEDG[8]" stuck at GND
    Warning (13410): Pin "VGA_SYNC" stuck at GND
Info: Generated suppressed messages file D:/PROGRAMING/fpga/Cursor/Cursor.map.smsg
Warning: Design contains 17 input pin(s) that do not drive logic
    Warning (15610): No output dependent on input pin "SW[0]"
    Warning (15610): No output dependent on input pin "SW[1]"
    Warning (15610): No output dependent on input pin "SW[2]"
    Warning (15610): No output dependent on input pin "SW[3]"
    Warning (15610): No output dependent on input pin "SW[4]"
    Warning (15610): No output dependent on input pin "SW[5]"
    Warning (15610): No output dependent on input pin "SW[6]"
    Warning (15610): No output dependent on input pin "SW[7]"
    Warning (15610): No output dependent on input pin "SW[8]"
    Warning (15610): No output dependent on input pin "SW[9]"
    Warning (15610): No output dependent on input pin "SW[10]"
    Warning (15610): No output dependent on input pin "SW[11]"
    Warning (15610): No output dependent on input pin "SW[12]"
    Warning (15610): No output dependent on input pin "SW[13]"
    Warning (15610): No output dependent on input pin "SW[14]"
    Warning (15610): No output dependent on input pin "SW[15]"
    Warning (15610): No output dependent on input pin "SW[16]"
Info: Implemented 381 device resources after synthesis - the final resource count might be different
    Info: Implemented 23 input pins
    Info: Implemented 44 output pins
    Info: Implemented 314 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 42 warnings
    Info: Allocated 144 megabytes of memory during processing
    Info: Processing ended: Wed Jul 16 17:25:02 2008
    Info: Elapsed time: 00:00:05


+------------------------------------------+
; Analysis & Synthesis Suppressed Messages ;
+------------------------------------------+
The suppressed messages can be found in D:/PROGRAMING/fpga/Cursor/Cursor.map.smsg.