clkdiv_6.v

来自「分频器」· Verilog 代码 · 共 28 行

module clkdiv_6(clk_in,reset,clk_out);
input clk_in,reset;
output clk_out;
reg clk_out;
reg[3:0] count;
always @(posedge clk_in)
  begin
    if(!reset)
      begin
        clk_out<=0;
        count<=0;
      end
     else if(count<2)
      begin
        clk_out<=clk_out;
        count=count+1;
      end
     else
      begin
        count<=0;
        clk_out<=~clk_out;
      end
end
endmodule