clk_div6.v

来自「分频器」· Verilog 代码 · 共 21 行

module clk_div6(clk,reset,count,clk_out);
input clk,reset;
output clk_out;
output count;
reg[9:0]  count;
reg clk_out;
always @(posedge clk or posedge reset)
if(reset)
begin
count<=0;
clk_out<=0;
end
else 
if(count==2)
begin 
count<=0;
clk_out<=~clk_out;
end
else count<=count+1;
endmodule