y.vhd

学习Xilinx公司开发软件ISE的基础资料

library LIB;
use LIB.SYNOPSYS.all; 
use LIB.AMD_PACK.all; 

entity Y is
  port(OPERATION : in Y_MUX_OPS; 
       DATA_IN   : in ADDRESS; 
       REGCNT_IN : in ADDRESS; 
       STACK_IN  : in ADDRESS; 
       UPC_IN    : in ADDRESS; 
       MUXOUT    : out ADDRESS); 
end Y; 

architecture Y_HDL of Y is 
begin 

  with OPERATION select 
    MUXOUT <= DATA_IN when SELECT_DATA, 
	      REGCNT_IN when SELECT_REGCNT, 
              STACK_IN when SELECT_STACK, 
	      UPC_IN when SELECT_UPC, 
              ADDRESS'(others => '0') when SELECT_NONE; 

end Y_HDL;