am2910.vhd

学习Xilinx公司开发软件ISE的基础资料

library LIB;
use LIB.synopsys_attributes.all;
use LIB.SYNOPSYS.all; 
use LIB.AMD_PACK.all; 

entity AM2910 is 
  port(D                       : in ADDRESS;
       INSTRUCTION             : in INSTRUCTION_OPS; 
       CONDITION_CODE          : in BIT; 
       CONDITION_CODE_ENABLE   : in BIT;
       CARRY_IN                : in BIT; 
       RELOAD                  : in BIT;
       ENABLE_Y                : in BIT; 
       CLOCK                   : in BIT; 
       Y_OUTPUT                : buffer ADDRESS; 
       OVERFLOW                : out BIT; 
       PIPELINE_ENABLE         : out BIT; 
       MAPPING_ROM_ENABLE      : out BIT; 
       INTERRUPT_DRIVER_ENABLE : out BIT); 
end AM2910; 

architecture HDL of AM2910 is 

  component CONTROL
    port(INSTRUCTION		: in INSTRUCTION_OPS; 
	 CONDITION_CODE		: in BIT; 
	 CONDITION_CODE_ENABLE	: in BIT; 
	 FORCE_LOAD		: in BIT; 
	 REGCNT_ZERO		: in BIT; 
	 UPC_CONTROL		: out UPC_OPS;
	 STACK_CONTROL		: out STACK_OPS; 
	 REGCNT_CONTROL		: out REGCNT_OPS; 
	 Y_CONTROL		: out Y_MUX_OPS; 
	 PIPELINE_ENABLE	: out BIT; 
	 MAPPING_ROM_ENABLE	: out BIT; 
	 INTERRUPT_VECTOR_ENABLE: out BIT); 
  end component; 
  
  component REGCNT 
    port(OPERATION	: in REGCNT_OPS;
	 DATA		: in ADDRESS; 
	 CLOCK		: in BIT; 
	 OUTPUT		: buffer ADDRESS; 
	 ZERO		: out BIT); 
  end component; 

  component STACK 
    port(OPERATION	: in STACK_OPS; 
	 VALUE		: in ADDRESS; 
	 CLOCK		: in BIT; 
	 OUTPUT_VALUE	: out ADDRESS; 
	 OVERFLOW	: out BIT); 
  end component; 

  component UPC 
    port(OPERATION	: in UPC_OPS; 
	 DATA		: in ADDRESS; 
	 CARRY_IN	: in BIT; 
	 CLOCK		: in BIT; 
	 OUTPUT		: buffer ADDRESS; 
	 OUTPUT_BAR	: out ADDRESS); 
  end component; 

  component Y  
    port(OPERATION	: in Y_MUX_OPS; 
	 DATA_IN	: in ADDRESS; 
	 REGCNT_IN	: in ADDRESS; 
	 STACK_IN	: in ADDRESS; 
	 UPC_IN		: in ADDRESS; 
	 MUXOUT		: out ADDRESS); 
  end component; 
  
  -- Top-level nets that connect major submodules 
  signal REGCNT_OP: REGCNT_OPS; 	-- Register/counter control signal
  signal STACK_OP: STACK_OPS; 		-- Stack control signal
  signal UPC_OP: UPC_OPS; 		-- UPC control signal
  signal Y_OP: Y_MUX_OPS; 		-- Mux control signal

  signal REGCNT_OUT: ADDRESS; 		-- Register/count output 
  signal REGCNT_ZERO: BIT; 		-- Register/counter zero flag 
  signal STACK_TOP: ADDRESS; 		-- Top of the stack
  signal UPC_OUT: ADDRESS; 		-- UPC output 
  signal UPC_OUT_BAR: ADDRESS; 		-- UPC output inverted
  signal TMP_Y_OUTPUT: ADDRESS; 	-- Local output signal

  -- The following attribute is supported after v3.4a
  -- attribute DONT_TOUCH of U1 : label is TRUE;
  -- attribute DONT_TOUCH of U2 : label is TRUE;
  -- attribute DONT_TOUCH of U3 : label is TRUE;
  -- attribute DONT_TOUCH of U4 : label is TRUE;
  -- attribute DONT_TOUCH of U5 : label is TRUE;

begin 

  U1: STACK port map(STACK_OP, UPC_OUT_BAR, CLOCK, STACK_TOP, OVERFLOW); 

  U2: UPC port map(UPC_OP, Y_OUTPUT, CARRY_IN, CLOCK, UPC_OUT, UPC_OUT_BAR); 

  U3: REGCNT port map(REGCNT_OP, D, CLOCK, REGCNT_OUT, REGCNT_ZERO); 

  U4: Y port map(Y_OP, D, REGCNT_OUT, STACK_TOP, UPC_OUT, TMP_Y_OUTPUT); 
  Y_OUTPUT <= TMP_Y_OUTPUT; 

  U5: CONTROL port map(INSTRUCTION, CONDITION_CODE,
		       CONDITION_CODE_ENABLE, RELOAD, REGCNT_ZERO, 
		       UPC_OP, STACK_OP, REGCNT_OP, Y_OP,
		       PIPELINE_ENABLE, MAPPING_ROM_ENABLE,
		       INTERRUPT_DRIVER_ENABLE); 

end HDL;