bts4.vhd

来自「学习Xilinx公司开发软件ISE的基础资料」· VHDL 代码 · 共 16 行

library LIB;
use LIB.SYNOPSYS.all; 
use LIB.AMD_PACK.all; 

entity BTS4 is
  port(A: in BIT; E: in BIT; Z: out BIT) ; 
end BTS4; 

architecture BTS4_struct of BTS4 is 
    component TBUF
      port(I: in BIT; T: in BIT; O: out BIT) ; 
    end component; 
begin 
  cell1 : TBUF port map(A, E, Z);
end BTS4_struct;