upc.vhd

来自「学习Xilinx公司开发软件ISE的基础资料」· VHDL 代码 · 共 30 行

library LIB;
use LIB.SYNOPSYS.all; 
use LIB.AMD_PACK.all; 

entity UPC is
  port( OPERATION  : in UPC_OPS; 
	DATA       : in ADDRESS; 
	CARRY_IN   : in BIT; 
	CLOCK      : in BIT; 
	OUTPUT	   : buffer ADDRESS; 
	OUTPUT_BAR : out ADDRESS); 
end UPC; 

architecture UPC_HDL of UPC is 
begin 

  process
  begin 
    wait until (not CLOCK'stable and CLOCK = '1'); 

    if OPERATION = COUNT then 
      OUTPUT <= DATA + CARRY_IN; 
    else 
      OUTPUT <= ADDRESS'(others => '0');
    end if; 
  end process; 

  OUTPUT_BAR <= not OUTPUT; 
end UPC_HDL;