alu.srr

学习Xilinx公司开发软件ISE的基础资料

Warning: Unrecognized command line switch ignored: -lcx:oPqEli{D
Starting:  j:\eda\synplicity\Synplify_70\bin\mbin\synplify.exe
Version:   7.0.2   
Date:      Fri Nov 08 09:08:25 2002
Arguments: -pro alu.prj -tcl alu_map.tcl -batch -launchmode -lcx:oPqEli{D
License: synplifypro_pc

Running synthesis on alu:alu_vlog

log file: "j:\project_navigator_demo\alu_vlog\alu.srr"

Running verilog Syntax check...
Verilog Compiler Completed

Verilog Compiler: 0 errors, 2 warnings, 1 note

Total: 0 errors, 2 warnings, 1 note
running FSM Explorer...
Fsm Explorer Completed

Fsm Explorer: 0 errors, 0 warnings, 0 notes

Total: 0 errors, 2 warnings, 1 note
Launching mapper in pro mode
Mapper Completed

Mapper: 0 errors, 1 warning, 2 notes

Total: 0 errors, 3 warnings, 3 notes
TCL script complete: "alu_map.tcl"
exit status=0


$ Start of Compile
#Fri Nov 08 09:08:25 2002

Synplicity Verilog Compiler, version 7.0.0, Build 130R, built Nov 16 2001
Copyright (C) 1994-2001, Synplicity Inc.  All Rights Reserved

@I::"J:\Project_Navigator_Demo\alu_vlog\ALU.V"
@W:"J:\Project_Navigator_Demo\alu_vlog\ALU.V":17:4:17:7|Case statement has both a full_case directive and a default clause.  The full_case directive is ignored.
Verilog syntax check successful!
Selecting top level module alu
Synthesizing module alu
@N:"J:\Project_Navigator_Demo\alu_vlog\ALU.V":23:20:23:25|Removing redundant assignment
@W:"J:\Project_Navigator_Demo\alu_vlog\ALU.V":29:4:29:7|Latch generated from always block for signal outp_a[7:0], probably caused by a missing assignment in an if or case stmt
@END
Process took 0.28 seconds realtime, 0.29 seconds cputime
Synplicity Xilinx Technology Mapper, version 7.0.0, Build 129R, built Nov 12 2001
Copyright (C) 1994-2001, Synplicity Inc.  All Rights Reserved
Reading constraint file: j:\project_navigator_demo\alu_vlog\alu.sdc

Running FSM Explorer ...

Did not find any FSM for encoding selection. Exiting ...

FSM Explorer successful!
Process took 0.401 seconds realtime, 0.4 seconds cputime
Synplicity Xilinx Technology Mapper, version 7.0.0, Build 129R, built Nov 12 2001
Copyright (C) 1994-2001, Synplicity Inc.  All Rights Reserved
Reading constraint file: j:\project_navigator_demo\alu_vlog\alu.sdc

Clock Buffers:
  Inserting Clock buffer for port clk,	TNM=clk

Net buffering Report for view:work.alu(verilog):
No nets needed buffering.

@N|The option to pack flops in the IOB has not been specified 
Writing Analyst data base j:\project_navigator_demo\alu_vlog\alu.srm
Writing EDIF Netlist and constraint files
Found clock clk with period 1000.00ns 
@W:"j:\project_navigator_demo\alu_vlog\alu.v":1:1:22:6|Net un1_outp_s25_0 appears to be a clock source which was not identified. Assuming default frequency. 


##### START TIMING REPORT #####
# Timing Report written on Fri Nov 08 09:08:29 2002
#


Top view:              alu
Slew propagation mode: worst
Paths requested:       5
Constraint File(s):    j:\project_navigator_demo\alu_vlog\alu.sdc
                       
@N| This timing report estimates place and route data. Please look at the place and route timing report for final timing.



Performance Summary 
*******************


Worst slack in design: 988.824
BLogParam: No file to write into.

                   Requested     Estimated     Requested     Estimated                 Clock   
Starting Clock     Frequency     Frequency     Period        Period        Slack       Type    
-----------------------------------------------------------------------------------------------
clk                1.0 MHz       344.8 MHz     1000.000      2.900         997.100     inferred
System             1.0 MHz       89.5 MHz      1000.000      11.176        988.824     system  
===============================================================================================



Clock Relationships
*******************

Starting     Ending        r/r           f/f           r/f           f/r   
Clock        Clock      time (ns)     time (ns)     time (ns)     time (ns)
---------------------------------------------------------------------------
clk          clk        1000.0        -             -             -        
===========================================================================



Interface Information 
*********************



Input Ports: 

Port          Starting            User           Arrival     Required            
Name          Reference           Constraint     Time        Time         Slack  
              Clock                                                              
---------------------------------------------------------------------------------
a[0]          System (rising)     NA             0.000       991.240      991.240
a[1]          System (rising)     NA             0.000       991.342      991.342
a[2]          System (rising)     NA             0.000       991.444      991.444
a[3]          System (rising)     NA             0.000       991.546      991.546
a[4]          System (rising)     NA             0.000       991.648      991.648
a[5]          System (rising)     NA             0.000       991.750      991.750
a[6]          System (rising)     NA             0.000       991.852      991.852
a[7]          System (rising)     NA             0.000       993.075      993.075
b[0]          System (rising)     NA             0.000       991.444      991.444
b[1]          System (rising)     NA             0.000       991.546      991.546
b[2]          System (rising)     NA             0.000       991.648      991.648
b[3]          System (rising)     NA             0.000       991.750      991.750
b[4]          System (rising)     NA             0.000       991.852      991.852
b[5]          System (rising)     NA             0.000       991.954      991.954
b[6]          System (rising)     NA             0.000       992.056      992.056
b[7]          System (rising)     NA             0.000       993.117      993.117
clk           NA                  NA             NA          NA           NA     
opcode[0]     System (rising)     NA             0.000       988.824      988.824
opcode[1]     System (rising)     NA             0.000       993.885      993.885
opcode[2]     System (rising)     NA             0.000       989.363      989.363
=================================================================================


Output Ports: 

Port          Starting            User           Arrival     Required            
Name          Reference           Constraint     Time        Time         Slack  
              Clock                                                              
---------------------------------------------------------------------------------
outp_a[0]     System (rising)     NA             5.800       1000.000     994.200
outp_a[1]     System (rising)     NA             5.800       1000.000     994.200
outp_a[2]     System (rising)     NA             5.800       1000.000     994.200
outp_a[3]     System (rising)     NA             5.800       1000.000     994.200
outp_a[4]     System (rising)     NA             5.800       1000.000     994.200
outp_a[5]     System (rising)     NA             5.800       1000.000     994.200
outp_a[6]     System (rising)     NA             5.800       1000.000     994.200
outp_a[7]     System (rising)     NA             5.800       1000.000     994.200
outp_s[0]     clk (rising)        NA             2.900       1000.000     997.100
outp_s[1]     clk (rising)        NA             2.900       1000.000     997.100
outp_s[2]     clk (rising)        NA             2.900       1000.000     997.100
outp_s[3]     clk (rising)        NA             2.900       1000.000     997.100
outp_s[4]     clk (rising)        NA             2.900       1000.000     997.100
outp_s[5]     clk (rising)        NA             2.900       1000.000     997.100
outp_s[6]     clk (rising)        NA             2.900       1000.000     997.100
outp_s[7]     clk (rising)        NA             2.900       1000.000     997.100
=================================================================================



====================================
Detailed Report for Clock: clk
====================================



Starting Points with worst slack 
********************************

                                               Arrival            
Instance      Type     Pin     Net             Time        Slack  
                                                                  
------------------------------------------------------------------
outp_s[0]     FDE      Q       outp_s_c[0]     0.000       997.100
outp_s[1]     FDE      Q       outp_s_c[1]     0.000       997.100
outp_s[2]     FDE      Q       outp_s_c[2]     0.000       997.100
outp_s[3]     FDE      Q       outp_s_c[3]     0.000       997.100
outp_s[4]     FDE      Q       outp_s_c[4]     0.000       997.100
outp_s[5]     FDE      Q       outp_s_c[5]     0.000       997.100
outp_s[6]     FDE      Q       outp_s_c[6]     0.000       997.100