top.vhd

学习Xilinx公司开发软件ISE的基础资料

-- Xilinx Vhdl produced by program ngd2vhdl F.28
-- Command: top.nga 
-- Input file: top.nga
-- Output file: top.vhd
-- Design name: top
-- Xilinx: J:/eda/Xilinx
-- # of Entities: 1
-- Device: 2v40cs144-5 (PRODUCTION 1.114 2002-12-13, STEPPING 1)

-- The output of ngd2vhdl is a simulation model. This file cannot be synthesized,
-- or used in any other manner other than simulation. This netlist uses simulation
-- primitives which may not represent the true implementation of the device, however
-- the netlist is functionally correct. Do not modify this file.

-- Model for  ROC (Reset-On-Configuration) Cell
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
entity ROC is
  generic (InstancePath: STRING := "*";
           WIDTH : Time := 100 ns);
  port(O : out std_ulogic := '1') ;
  attribute VITAL_LEVEL0 of ROC : entity is TRUE;
end ROC;

architecture ROC_V of ROC is
attribute VITAL_LEVEL0 of ROC_V : architecture is TRUE;
begin
  ONE_SHOT : process
  begin
    if (WIDTH <= 0 ns) then
       assert FALSE report
       "*** Error: a positive value of WIDTH must be specified ***"
       severity failure;
    else
       wait for WIDTH;
       O <= '0';
    end if;
    wait;
  end process ONE_SHOT;
end ROC_V;

-- Model for  TOC (Tristate-On-Configuration) Cell
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
entity TOC is
  generic (InstancePath: STRING := "*";
           WIDTH : Time := 0 ns);
  port(O : out std_ulogic := '0');
  attribute VITAL_LEVEL0 of TOC : entity is TRUE;
end TOC;

architecture TOC_V of TOC is
attribute VITAL_LEVEL0 of TOC_V : architecture is TRUE;
begin
  ONE_SHOT : process
  begin
    O <= '1';
    if (WIDTH <= 0 ns) then
       O <= '0';
    else
       wait for WIDTH;
       O <= '0';
    end if;
    wait;
  end process ONE_SHOT;
end TOC_V;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;
entity top is
  port (
    modc_out : out STD_LOGIC; 
    modb_clk_pad : in STD_LOGIC := 'X'; 
    mod_c_out : out STD_LOGIC; 
    obuft_out : out STD_LOGIC; 
    modb_out : out STD_LOGIC; 
    modc_data : in STD_LOGIC := 'X'; 
    moda_clk_pad : in STD_LOGIC := 'X'; 
    ipad_dll_clk_in : in STD_LOGIC := 'X'; 
    modb_data : in STD_LOGIC := 'X'; 
    modc_clk_pad : in STD_LOGIC := 'X'; 
    moda_data : in STD_LOGIC := 'X'; 
    top2a_c : in STD_LOGIC := 'X'; 
    top2b : in STD_LOGIC := 'X'; 
    dll_rst : in STD_LOGIC := 'X'; 
    moda_out : out STD_LOGIC 
  );
end top;

architecture STRUCTURE of top is
  component ROC
    generic (InstancePath: STRING := "*";
             WIDTH : Time := 100 ns);
    port (O : out STD_ULOGIC := '1');
  end component;
  component TOC
    generic (InstancePath: STRING := "*";
             WIDTH : Time := 0 ns);
    port (O : out STD_ULOGIC := '1');
  end component;
  signal moda_clk : STD_LOGIC; 
  signal instance_a_Q3_OUT : STD_LOGIC; 
  signal instance_a_Q0_OUT : STD_LOGIC; 
  signal instance_a_Q1_OUT : STD_LOGIC; 
  signal instance_a_Q2_OUT : STD_LOGIC; 
  signal instance_a_N_11_i : STD_LOGIC; 
  signal a2c : STD_LOGIC; 
  signal clk_top : STD_LOGIC; 
  signal instance_b_Q0_OUT : STD_LOGIC; 
  signal instance_b_Q1_OUT : STD_LOGIC; 
  signal instance_b_Q2_OUT : STD_LOGIC; 
  signal instance_b_Q3_OUT : STD_LOGIC; 
  signal instance_b_AND4_OUT : STD_LOGIC; 
  signal b2a : STD_LOGIC; 
  signal instance_b_OR4_OUT : STD_LOGIC; 
  signal instance_b_MODB_OUT : STD_LOGIC; 
  signal modc_clk : STD_LOGIC; 
  signal instance_c_Q0_OUT : STD_LOGIC; 
  signal instance_c_Q1_OUT : STD_LOGIC; 
  signal instance_c_Q2_OUT : STD_LOGIC; 
  signal instance_c_Q3_OUT : STD_LOGIC; 
  signal instance_c_OR4_OUT : STD_LOGIC; 
  signal instance_c_C2TOP_OUT : STD_LOGIC; 
  signal instance_c_AND4_OUT : STD_LOGIC; 
  signal c2and2 : STD_LOGIC; 
  signal instance_a_G_7 : STD_LOGIC; 
  signal a2top_obuft_i : STD_LOGIC; 
  signal top2a_c_c : STD_LOGIC; 
  signal bufg_modb_IBUFG : STD_LOGIC; 
  signal dll_rst_c : STD_LOGIC; 
  signal instance_a_MODA_OUT : STD_LOGIC; 
  signal bufg_moda_IBUFG : STD_LOGIC; 
  signal bufg_modc_IBUFG : STD_LOGIC; 
  signal instance_c_MODC_OUT : STD_LOGIC; 
  signal b2top_obuft_t : STD_LOGIC; 
  signal GLOBAL_LOGIC1 : STD_LOGIC; 
  signal dll_clk_out : STD_LOGIC; 
  signal modb_clk : STD_LOGIC; 
  signal b2c : STD_LOGIC; 
  signal c2a : STD_LOGIC; 
  signal a2b : STD_LOGIC; 
  signal GSR : STD_LOGIC; 
  signal GTS : STD_LOGIC; 
  signal dll_1_CLKIN_BUF : STD_LOGIC; 
  signal dll_1_CLKFB_BUF : STD_LOGIC; 
  signal dll_1_PSINCDECINVNOT : STD_LOGIC; 
  signal dll_1_PSENINVNOT : STD_LOGIC; 
  signal dll_1_PSCLKINVNOT : STD_LOGIC; 
  signal dll_1_CLK90 : STD_LOGIC; 
  signal dll_1_CLK180 : STD_LOGIC; 
  signal dll_1_CLK270 : STD_LOGIC; 
  signal dll_1_CLK2X : STD_LOGIC; 
  signal dll_1_CLK2X180 : STD_LOGIC; 
  signal dll_1_CLKDV : STD_LOGIC; 
  signal dll_1_CLKFX : STD_LOGIC; 
  signal dll_1_CLKFX180 : STD_LOGIC; 
  signal dll_1_LOCKED : STD_LOGIC; 
  signal dll_1_PSDONE : STD_LOGIC; 
  signal dll_1_STATUS7 : STD_LOGIC; 
  signal dll_1_STATUS6 : STD_LOGIC; 
  signal dll_1_STATUS5 : STD_LOGIC; 
  signal dll_1_STATUS4 : STD_LOGIC; 
  signal dll_1_STATUS3 : STD_LOGIC; 
  signal dll_1_STATUS2 : STD_LOGIC; 
  signal dll_1_STATUS1 : STD_LOGIC; 
  signal dll_1_STATUS0 : STD_LOGIC; 
  signal bufg_modb_BUFG_S_INVNOT : STD_LOGIC; 
  signal globalclk_S_INVNOT : STD_LOGIC; 
  signal bufg_modc_BUFG_S_INVNOT : STD_LOGIC; 
  signal bufg_moda_BUFG_S_INVNOT : STD_LOGIC; 
  signal instance_a_MODA_OUT_CLKINV : STD_LOGIC; 
  signal instance_a_MODA_OUT_SRFFMUX : STD_LOGIC; 
  signal instance_a_MODA_OUT_DYMUX : STD_LOGIC; 
  signal instance_a_Q0_OUT_CLKINV : STD_LOGIC; 
  signal instance_a_Q0_OUT_DYMUX : STD_LOGIC; 
  signal instance_c_Q0_OUT_CLKINV : STD_LOGIC; 
  signal instance_c_Q0_OUT_DYMUX : STD_LOGIC; 
  signal instance_c_Q2_OUT_CLKINV : STD_LOGIC; 
  signal instance_c_Q2_OUT_DYMUX : STD_LOGIC; 
  signal instance_b_Q0_OUT_CLKINV : STD_LOGIC; 
  signal instance_b_Q0_OUT_DYMUX : STD_LOGIC; 
  signal b2c_CLKINV : STD_LOGIC; 
  signal b2c_DYMUX : STD_LOGIC; 
  signal instance_a_Q1_OUT_CLKINV : STD_LOGIC; 
  signal instance_a_Q1_OUT_DYMUX : STD_LOGIC; 
  signal instance_a_Q2_OUT_CLKINV : STD_LOGIC; 
  signal instance_a_Q2_OUT_DYMUX : STD_LOGIC; 
  signal c2a_CLKINV : STD_LOGIC; 
  signal c2a_DYMUX : STD_LOGIC; 
  signal b2top_obuft_t_CLKINV : STD_LOGIC; 
  signal b2top_obuft_t_DYMUX : STD_LOGIC; 
  signal instance_b_Q1_OUT_CLKINV : STD_LOGIC; 
  signal instance_b_Q1_OUT_DYMUX : STD_LOGIC; 
  signal a_and_c_G : STD_LOGIC; 
  signal instance_a_Q3_OUT_CLKINV : STD_LOGIC; 
  signal instance_a_Q3_OUT_DYMUX : STD_LOGIC; 
  signal instance_b_Q2_OUT_CLKINV : STD_LOGIC; 
  signal instance_b_Q2_OUT_DYMUX : STD_LOGIC; 
  signal instance_c_Q1_OUT_CLKINV : STD_LOGIC; 
  signal instance_c_Q1_OUT_DYMUX : STD_LOGIC; 
  signal instance_c_Q3_OUT_CLKINV : STD_LOGIC; 
  signal instance_c_Q3_OUT_DYMUX : STD_LOGIC; 
  signal instance_b_Q3_OUT_CLKINV : STD_LOGIC; 
  signal instance_b_Q3_OUT_DYMUX : STD_LOGIC; 
  signal instance_c_MODC_OUT_CLKINV : STD_LOGIC; 
  signal instance_c_MODC_OUT_DYMUX : STD_LOGIC; 
  signal a2b_CLKINV : STD_LOGIC; 
  signal a2b_SRINVNOT : STD_LOGIC; 
  signal a2b_SRFFMUX : STD_LOGIC; 
  signal a2b_DYMUX : STD_LOGIC; 
  signal b2c_FFY_RST : STD_LOGIC; 
  signal instance_c_Q0_OUT_FFY_RST : STD_LOGIC; 
  signal instance_a_Q0_OUT_FFY_RST : STD_LOGIC; 
  signal instance_b_Q1_OUT_FFY_RST : STD_LOGIC; 
  signal instance_a_Q3_OUT_FFY_RST : STD_LOGIC; 
  signal instance_b_Q0_OUT_FFY_RST : STD_LOGIC; 
  signal c2a_FFY_RST : STD_LOGIC; 
  signal instance_b_Q2_OUT_FFY_RST : STD_LOGIC; 
  signal instance_a_Q2_OUT_FFY_RST : STD_LOGIC; 
  signal instance_c_MODC_OUT_FFY_RST : STD_LOGIC; 
  signal instance_c_Q3_OUT_FFY_RST : STD_LOGIC; 
  signal instance_c_Q2_OUT_FFY_RST : STD_LOGIC; 
  signal b2top_obuft_t_FFY_RST : STD_LOGIC; 
  signal a2c_CLKINV : STD_LOGIC; 
  signal a2c_SRFFMUX : STD_LOGIC; 
  signal a2c_G : STD_LOGIC; 
  signal a2c_DYMUX : STD_LOGIC; 
  signal b2a_CLKINV : STD_LOGIC; 
  signal b2a_G : STD_LOGIC; 
  signal b2a_DYMUX : STD_LOGIC; 
  signal b2a_F : STD_LOGIC; 
  signal b2a_DXMUX : STD_LOGIC; 
  signal b2a_FFX_RST : STD_LOGIC; 
  signal b2a_FFY_RST : STD_LOGIC; 
  signal instance_c_C2TOP_OUT_CLKINV : STD_LOGIC; 
  signal instance_c_C2TOP_OUT_G : STD_LOGIC; 
  signal instance_c_C2TOP_OUT_DYMUX : STD_LOGIC; 
  signal instance_c_C2TOP_OUT_FFY_RST : STD_LOGIC; 
  signal c2and2_CLKINV : STD_LOGIC; 
  signal c2and2_G : STD_LOGIC; 
  signal c2and2_DYMUX : STD_LOGIC; 
  signal c2and2_FFY_RST : STD_LOGIC; 
  signal a2top_obuft_i_CLKINV : STD_LOGIC; 
  signal a2top_obuft_i_SRINVNOT : STD_LOGIC; 
  signal a2top_obuft_i_SRFFMUX : STD_LOGIC; 
  signal a2top_obuft_i_G : STD_LOGIC; 
  signal a2top_obuft_i_DYMUX : STD_LOGIC; 
  signal instance_a_Q1_OUT_FFY_RST : STD_LOGIC; 
  signal moda_out_O : STD_LOGIC; 
  signal moda_out_GTS_OR_T : STD_LOGIC; 
  signal moda_out_ENABLE : STD_LOGIC; 
  signal modb_out_O : STD_LOGIC; 
  signal modb_out_GTS_OR_T : STD_LOGIC; 
  signal modb_out_ENABLE : STD_LOGIC; 
  signal mod_c_out_O : STD_LOGIC; 
  signal mod_c_out_GTS_OR_T : STD_LOGIC; 
  signal mod_c_out_ENABLE : STD_LOGIC; 
  signal modc_out_O : STD_LOGIC; 
  signal modc_out_GTS_OR_T : STD_LOGIC; 
  signal modc_out_ENABLE : STD_LOGIC; 
  signal obuft_out_T : STD_LOGIC; 
  signal obuft_out_O : STD_LOGIC; 
  signal obuft_out_GTS_OR_T : STD_LOGIC; 
  signal obuft_out_ENABLE : STD_LOGIC; 
  signal instance_b_Q3_OUT_FFY_RST : STD_LOGIC; 
  signal instance_c_Q1_OUT_FFY_RST : STD_LOGIC; 
  signal GND : STD_LOGIC; 
  signal VCC : STD_LOGIC; 
begin
  GLOBAL_LOGIC1_ONE : X_ONE
    port map (
      O => GLOBAL_LOGIC1
    );
  ibuf_dll : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => ipad_dll_clk_in,
      O => dll_1_CLKIN_BUF
    );
  dll_1_CLKFB_BUF_0 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => clk_top,
      O => dll_1_CLKFB_BUF
    );
  dll_1 : X_DCM
    generic map(
      DUTY_CYCLE_CORRECTION => TRUE,
      CLKDV_DIVIDE => 2.0,
      CLKFX_DIVIDE => 1,
      CLKFX_MULTIPLY => 4,
      CLKOUT_PHASE_SHIFT => "NONE",
      CLK_FEEDBACK => "1X",
      DLL_FREQUENCY_MODE => "LOW",
      PHASE_SHIFT => 0,
      MAXPERCLKIN => 41668 ps,
      MAXPERPSCLK => 999998999 ps
    )
    port map (
      CLKIN => dll_1_CLKIN_BUF,
      CLKFB => dll_1_CLKFB_BUF,
      DSSEN => GLOBAL_LOGIC1,
      RST => dll_rst_c,
      PSINCDEC => dll_1_PSINCDECINVNOT,
      PSEN => dll_1_PSENINVNOT,
      PSCLK => dll_1_PSCLKINVNOT,
      CLK0 => dll_clk_out,
      CLK90 => dll_1_CLK90,
      CLK180 => dll_1_CLK180,
      CLK270 => dll_1_CLK270,
      CLK2X => dll_1_CLK2X,
      CLK2X180 => dll_1_CLK2X180,
      CLKDV => dll_1_CLKDV,
      CLKFX => dll_1_CLKFX,
      CLKFX180 => dll_1_CLKFX180,
      LOCKED => dll_1_LOCKED,
      PSDONE => dll_1_PSDONE,
      STATUS(7) => dll_1_STATUS7,
      STATUS(6) => dll_1_STATUS6,
      STATUS(5) => dll_1_STATUS5,
      STATUS(4) => dll_1_STATUS4,
      STATUS(3) => dll_1_STATUS3,
      STATUS(2) => dll_1_STATUS2,
      STATUS(1) => dll_1_STATUS1,
      STATUS(0) => dll_1_STATUS0
    );
  dll_1_PSINCDECINV : X_INV
    port map (
      I => GLOBAL_LOGIC1,
      O => dll_1_PSINCDECINVNOT
    );
  dll_1_PSENINV : X_INV
    port map (
      I => GLOBAL_LOGIC1,
      O => dll_1_PSENINVNOT
    );
  dll_1_PSCLKINV : X_INV
    port map (
      I => GLOBAL_LOGIC1,
      O => dll_1_PSCLKINVNOT
    );
  bufg_modb_BUFG_SINV : X_INV
    port map (
      I => GLOBAL_LOGIC1,
      O => bufg_modb_BUFG_S_INVNOT
    );
  bufg_modb_BUFG : X_BUFGMUX
    port map (
      I0 => bufg_modb_IBUFG,
      I1 => GND,
      S => bufg_modb_BUFG_S_INVNOT,
      O => modb_clk,
      GSR => GSR
    );
  globalclk_SINV : X_INV
    port map (
      I => GLOBAL_LOGIC1,
      O => globalclk_S_INVNOT
    );
  globalclk : X_BUFGMUX
    port map (
      I0 => dll_clk_out,
      I1 => GND,
      S => globalclk_S_INVNOT,
      O => clk_top,
      GSR => GSR
    );
  bufg_modc_BUFG_SINV : X_INV
    port map (
      I => GLOBAL_LOGIC1,
      O => bufg_modc_BUFG_S_INVNOT
    );
  bufg_modc_BUFG : X_BUFGMUX
    port map (
      I0 => bufg_modc_IBUFG,
      I1 => GND,
      S => bufg_modc_BUFG_S_INVNOT,
      O => modc_clk,
      GSR => GSR
    );
  bufg_moda_BUFG_SINV : X_INV
    port map (
      I => GLOBAL_LOGIC1,
      O => bufg_moda_BUFG_S_INVNOT
    );
  bufg_moda_BUFG : X_BUFGMUX
    port map (
      I0 => bufg_moda_IBUFG,
      I1 => GND,
      S => bufg_moda_BUFG_S_INVNOT,
      O => moda_clk,
      GSR => GSR
    );
  instance_a_MODA_OUT_CLKINV_1 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => clk_top,
      O => instance_a_MODA_OUT_CLKINV
    );
  instance_a_MODA_OUT_SRFFMUX_2 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => instance_a_Q3_OUT,
      O => instance_a_MODA_OUT_SRFFMUX
    );
  instance_a_MODA_OUT_DYMUX_3 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => instance_a_N_11_i,
      O => instance_a_MODA_OUT_DYMUX
    );
  instance_a_Q0_OUT_CLKINV_4 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => clk_top,
      O => instance_a_Q0_OUT_CLKINV
    );
  instance_a_moda_data_ibuf : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => moda_data,
      O => instance_a_Q0_OUT_DYMUX
    );
  instance_c_Q0_OUT_CLKINV_5 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => clk_top,
      O => instance_c_Q0_OUT_CLKINV
    );
  instance_c_modc_data_ibuf : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => modc_data,
      O => instance_c_Q0_OUT_DYMUX
    );
  instance_c_Q2_OUT_CLKINV_6 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => clk_top,
      O => instance_c_Q2_OUT_CLKINV
    );
  instance_c_Q2_OUT_DYMUX_7 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => top2a_c_c,
      O => instance_c_Q2_OUT_DYMUX
    );
  instance_b_Q0_OUT_CLKINV_8 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => clk_top,
      O => instance_b_Q0_OUT_CLKINV
    );
  instance_b_modb_data_ibuf : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => modb_data,
      O => instance_b_Q0_OUT_DYMUX
    );
  b2c_CLKINV_9 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => modb_clk,
      O => b2c_CLKINV
    );
  b2c_DYMUX_10 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => instance_b_OR4_OUT,
      O => b2c_DYMUX
    );
  instance_a_Q1_OUT_CLKINV_11 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => moda_clk,
      O => instance_a_Q1_OUT_CLKINV