📄 top_routed.par
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Phase 3.23WARNING:Place:35 - A clock IOB / clock component pair have been found that are
not placed at an optimal clock IOB / clock site pair. The clock component
<bufg_modc/BUFG> is placed at site BUFGMUX1P. The clock IO site that is
paired with this clock buffer site is A8. The IO component modc_clk_pad is
placed at site B7. This will not allow the use of the fast path between the
IO and the Clock buffer. You may want to analyze why this problem exists and
correct it. This is not an error so processing will continue.WARNING:Place:35 - A clock IOB / clock component pair have been found that are
not placed at an optimal clock IOB / clock site pair. The clock component
<bufg_moda/BUFG> is placed at site BUFGMUX7P. The clock IO site that is
paired with this clock buffer site is C6. The IO component moda_clk_pad is
placed at site D6. This will not allow the use of the fast path between the
IO and the Clock buffer. You may want to analyze why this problem exists and
correct it. This is not an error so processing will continue.Phase 3.23 (Checksum:1c9c37d) REAL time: 4 secs Phase 4.8Phase 4.8 (Checksum:98b6d7) REAL time: 4 secs Phase 5.5Phase 5.5 (Checksum:2faf07b) REAL time: 4 secs Phase 6.18Phase 6.18 (Checksum:39386fa) REAL time: 4 secs Phase 7.24Phase 7.24 (Checksum:42c1d79) REAL time: 4 secs Writing design to file top_routed.ncd.Total REAL time to placer completion: 4 secs Total CPU time to placer completion: 4 secs Starting Router REAL time: 5 secs Phase 1: 44 unrouted; REAL time: 5 secs Phase 2: 12 unrouted; REAL time: 5 secs Phase 3: 1 unrouted; (0) REAL time: 5 secs Phase 4: 1 unrouted; (0) REAL time: 5 secs Phase 5: 1 unrouted; (0) REAL time: 5 secs Phase 6: 0 unrouted; (0) REAL time: 5 secs Finished Router REAL time: 5 secs Total REAL time to router completion: 5 secs Total CPU time to router completion: 5 secs Generating "par" statistics.**************************Generating Clock Report**************************+----------------------------+----------+--------+------------+-------------+| Clock Net | Resource | Fanout |Max Skew(ns)|Max Delay(ns)|+----------------------------+----------+--------+------------+-------------+| moda_clk | Global | 4 | 0.001 | 0.570 |+----------------------------+----------+--------+------------+-------------+| clk_top | Global | 12 | 0.013 | 0.570 |+----------------------------+----------+--------+------------+-------------+| modc_clk | Global | 4 | 0.002 | 0.562 |+----------------------------+----------+--------+------------+-------------+| modb_clk | Global | 4 | 0.000 | 0.559 |+----------------------------+----------+--------+------------+-------------+ The Delay Summary Report The Score for this design is: 82The Number of signals not completely routed for this design is: 0 The Average Connection Delay for this design is: 0.582 ns The Maximum Pin Delay is: 1.469 ns The Average Connection Delay on the 10 Worst Nets is: 1.199 ns Listing Pin Delays by value: (ns) d < 1.00 < d < 2.00 < d < 3.00 < d < 4.00 < d < 5.00 d >= 5.00 --------- --------- --------- --------- --------- --------- 87 9 0 0 0 0Timing Score: 0Asterisk (*) preceding a constraint indicates it was not met.-------------------------------------------------------------------------------- Constraint | Requested | Actual | Logic | | | Levels-------------------------------------------------------------------------------- TS_P2P = MAXDELAY FROM TIMEGRP "PADS" TO | | | TIMEGRP "PADS" 20 nS | | | -------------------------------------------------------------------------------- TS_ipad_dll_clk_in = PERIOD TIMEGRP "ipad | 20.000ns | 2.263ns | 1 _dll_clk_in" 20 nS HIGH 50.000000 % | | | -------------------------------------------------------------------------------- COMP "modc_data" OFFSET = IN 10 nS BEFOR | 10.000ns | 1.586ns | 1 E COMP "ipad_dll_clk_in" | | | -------------------------------------------------------------------------------- COMP "mod_c_out" OFFSET = OUT 10 nS AFTE | | | R COMP "ipad_dll_clk_in" | | | -------------------------------------------------------------------------------- COMP "modc_out" OFFSET = OUT 20 nS AFTER | | | COMP "ipad_dll_clk_in" | | | -------------------------------------------------------------------------------- COMP "modc_out" OFFSET = OUT 10 nS AFTER | 10.000ns | 6.553ns | 1 COMP "ipad_dll_clk_in" | | | -------------------------------------------------------------------------------- COMP "top2b" OFFSET = IN 10 nS BEFORE CO | 10.000ns | 1.580ns | 1 MP "ipad_dll_clk_in" | | | -------------------------------------------------------------------------------- COMP "modb_data" OFFSET = IN 10 nS BEFOR | 10.000ns | 1.312ns | 1 E COMP "ipad_dll_clk_in" | | | -------------------------------------------------------------------------------- COMP "modb_out" OFFSET = OUT 10 nS AFTER | 10.000ns | 6.555ns | 1 COMP "ipad_dll_clk_in" | | | -------------------------------------------------------------------------------- COMP "moda_out" OFFSET = OUT 10 nS AFTER | 10.000ns | 6.556ns | 1 COMP "ipad_dll_clk_in" | | | -------------------------------------------------------------------------------- COMP "moda_data" OFFSET = IN 10 nS BEFOR | 10.000ns | 1.840ns | 1 E COMP "ipad_dll_clk_in" | | | -------------------------------------------------------------------------------- COMP "dll_rst" OFFSET = IN 10 nS BEFORE | | | COMP "ipad_dll_clk_in" | | | -------------------------------------------------------------------------------- COMP "top2a_c" OFFSET = IN 10 nS BEFORE | 10.000ns | 1.586ns | 1 COMP "ipad_dll_clk_in" | | | -------------------------------------------------------------------------------- COMP "modc_clk_pad" OFFSET = IN 10 nS BE | | | FORE COMP "ipad_dll_clk_in" | | | -------------------------------------------------------------------------------- COMP "moda_clk_pad" OFFSET = IN 10 nS BE | | | FORE COMP "ipad_dll_clk_in" | | | -------------------------------------------------------------------------------- COMP "obuft_out" OFFSET = OUT 10 nS AFTE | | | R COMP "ipad_dll_clk_in" | | | -------------------------------------------------------------------------------- COMP "modb_clk_pad" OFFSET = IN 10 nS BE | | | FORE COMP "ipad_dll_clk_in" | | | -------------------------------------------------------------------------------- OFFSET = IN 10 nS BEFORE COMP "ipad_dll_ | | | clk_in" | | | -------------------------------------------------------------------------------- OFFSET = OUT 10 nS AFTER COMP "ipad_dll_ | | | clk_in" | | | --------------------------------------------------------------------------------All constraints were met.All signals are completely routed.Total REAL time to par completion: 5 secs Total CPU time to par completion: 5 secs Placement: Completed - No errors found.Routing: Completed - No errors found.Timing: Completed - No errors found.Writing design to file top_routed.ncd.PAR done.⌨️ 快捷键说明
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