top_routed.par

学习Xilinx公司开发软件ISE的基础资料

Release 5.2i - Par F.28
Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.


    ::  Thu Mar 27 16:08:55 2003


par -w top.ncd top_routed.ncd 


Constraints file: top.pcf

Loading device database for application par from file "top.ncd".
   "top" is an NCD, version 2.37, device xc2v40, package cs144, speed -5
Loading device for application par from file '2v40.nph' in environment
J:/eda/Xilinx.
The STEPPING level for this design is 1.
Device speed data version:  PRODUCTION 1.114 2002-12-13.


Resolved that IOB <top2a_c> must be placed at site A4.
Resolved that IOB <modb_clk_pad> must be placed at site D7.
Resolved that IOB <dll_rst> must be placed at site A3.
Resolved that IOB <moda_out> must be placed at site D5.
Resolved that IOB <modb_data> must be placed at site C6.
Resolved that IOB <ipad_dll_clk_in> must be placed at site B4.
Resolved that IOB <top2b> must be placed at site A6.
Resolved that IOB <modb_out> must be placed at site B6.
Resolved that IOB <mod_c_out> must be placed at site C8.
Resolved that IOB <moda_clk_pad> must be placed at site D6.
Resolved that IOB <modc_clk_pad> must be placed at site B7.
Resolved that IOB <modc_out> must be placed at site B8.
Resolved that IOB <obuft_out> must be placed at site C4.
Resolved that IOB <modc_data> must be placed at site A8.
Resolved that IOB <moda_data> must be placed at site A5.
Resolved that DCM <dll_1> must be placed at site DCM_X0Y1.
Resolved that BUFGMUX <bufg_modb/BUFG> must be placed at site BUFGMUX4S.
Resolved that BUFGMUX <globalclk> must be placed at site BUFGMUX6S.
Resolved that BUFGMUX <bufg_modc/BUFG> must be placed at site BUFGMUX1P.
Resolved that BUFGMUX <bufg_moda/BUFG> must be placed at site BUFGMUX7P.
Resolved that SLICE <a_and_c> must be placed at site SLICE_X7Y15.


Starting Guide File Processing.

Loading device database for application par from file
"\example-8-1\modular_design\pims/module_a/module_a.ncd".
   "top" is an NCD, version 2.37, device xc2v40, package cs144, speed -5
The STEPPING level for this design is 1.

Loading device database for application par from file
"\example-8-1\modular_design\pims/module_b/module_b.ncd".
   "top" is an NCD, version 2.37, device xc2v40, package cs144, speed -5
The STEPPING level for this design is 1.

Loading device database for application par from file
"\example-8-1\modular_design\pims/module_c/module_c.ncd".
   "top" is an NCD, version 2.37, device xc2v40, package cs144, speed -5
The STEPPING level for this design is 1.

Finished Guide File Processing.

Xilinx Place and Route Guide Results File
=========================================

Guide Summary Report:

Design Totals:
  Components:
    Name matched:                            31 out of    44   70%
    Total guided:                            31 out of    31  100%

  Signals:
    LOGIC0/LOGIC1 nets ignored:               1 out of    47
    Name matched:                            46 out of    46  100%
      Rejected Unrouted Nets:                 2 out of    46
      Rejected Port Nets:                    14 out of    46
    Total guided:                            32 out of    46   69%


Guide file: "\example-8-1\modular_design\pims/module_a/module_a.ncd"       
Guide mode: "exact"

  Components:
    Name matched:                            10 out of    29   34%
    Total guided:                             8 out of    10   80%

  Signals:
    LOGIC0/LOGIC1 nets ignored:               2 out of    40
    Name matched:                            27 out of    38   71%
      Rejected Unrouted Nets:                 1 out of    27
      Rejected Port Nets:                     8 out of    27
    Total guided:                            14 out of    27   51%

Guide file: "\example-8-1\modular_design\pims/module_b/module_b.ncd"       
Guide mode: "exact"

  Components:
    Name matched:                            10 out of    28   35%
    Total guided:                             7 out of    10   69%

  Signals:
    LOGIC0/LOGIC1 nets ignored:               2 out of    37
    Name matched:                            27 out of    35   77%
      Rejected Port Nets:                     7 out of    27
    Total guided:                             9 out of    27   33%

Guide file: "\example-8-1\modular_design\pims/module_c/module_c.ncd"       
Guide mode: "exact"

  Components:
    Name matched:                            11 out of    29   37%
    Total guided:                             8 out of    11   72%

  Signals:
    LOGIC0/LOGIC1 nets ignored:               2 out of    39
    Name matched:                            28 out of    37   75%
      Rejected Unrouted Nets:                 1 out of    28
      Rejected Port Nets:                     7 out of    28
    Total guided:                             9 out of    28   32%

For a detailed guide report refer to the "top_routed.grf" file.

Device utilization summary:

   Number of External IOBs            15 out of 88     17%
      Number of LOCed External IOBs   15 out of 15    100%

   Number of SLICEs                   24 out of 256     9%

   Number of BUFGMUXs                  4 out of 16     25%
   Number of DCMs                      1 out of 4      25%



Overall effort level (-ol):   2 (default)
Placer effort level (-pl):    2 (default)
Placer cost table entry (-t): 1
Router effort level (-rl):    2 (default)

Starting initial Timing Analysis.  REAL time: 0 secs 
WARNING:Timing:2666 - Constraint ignored: TS_P2P = MAXDELAY FROM TIMEGRP "PADS"
   TO TIMEGRP "PADS" 20 nS  ; 

WARNING:Timing:2667 - ipad_dll_clk_in does not clock data to mod_c_out
WARNING:Timing:2666 - Constraint ignored: COMP "mod_c_out" OFFSET = OUT 10 nS 
   AFTER COMP "ipad_dll_clk_in" ;

WARNING:Timing:2664 - ipad_dll_clk_in does not clock data from dll_rst
WARNING:Timing:2666 - Constraint ignored: COMP "dll_rst" OFFSET = IN 10 nS 
   BEFORE COMP "ipad_dll_clk_in" ;

WARNING:Timing:2664 - ipad_dll_clk_in does not clock data from modc_clk_pad
WARNING:Timing:2666 - Constraint ignored: COMP "modc_clk_pad" OFFSET = IN 10 nS 
   BEFORE COMP "ipad_dll_clk_in" ;

WARNING:Timing:2664 - ipad_dll_clk_in does not clock data from moda_clk_pad
WARNING:Timing:2666 - Constraint ignored: COMP "moda_clk_pad" OFFSET = IN 10 nS 
   BEFORE COMP "ipad_dll_clk_in" ;

WARNING:Timing:2667 - ipad_dll_clk_in does not clock data to obuft_out
WARNING:Timing:2666 - Constraint ignored: COMP "obuft_out" OFFSET = OUT 10 nS 
   AFTER COMP "ipad_dll_clk_in" ;

WARNING:Timing:2664 - ipad_dll_clk_in does not clock data from modb_clk_pad
WARNING:Timing:2666 - Constraint ignored: COMP "modb_clk_pad" OFFSET = IN 10 nS 
   BEFORE COMP "ipad_dll_clk_in" ;

Finished initial Timing Analysis.  REAL time: 4 secs 


Phase 1.1
Phase 1.1 (Checksum:98972f) REAL time: 4 secs 

WARNING: clk logic <ipad_dll_clk_in> locked elsewhere <B4>.
WARNING: clk logic <moda_clk_pad> locked elsewhere <D6>.