top_routed.grf

学习Xilinx公司开发软件ISE的基础资料

Release 5.2i - Par F.28
Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Thu Mar 27 16:08:56 2003

Xilinx Place and Route Guide Results File
=========================================

Guide Summary Report:

Design Totals:
  Components:
    Name matched:                            31 out of    44   70%
    Total guided:                            31 out of    31  100%

  Signals:
    LOGIC0/LOGIC1 nets ignored:               1 out of    47
    Name matched:                            46 out of    46  100%
      Rejected Unrouted Nets:                 2 out of    46
      Rejected Port Nets:                    14 out of    46
    Total guided:                            32 out of    46   69%


Guide file: "\example-8-1\modular_design\pims/module_a/module_a.ncd"       
Guide mode: "exact"

  Components:
    Name matched:                            10 out of    29   34%
    Total guided:                             8 out of    10   80%

  Signals:
    LOGIC0/LOGIC1 nets ignored:               2 out of    40
    Name matched:                            27 out of    38   71%
      Rejected Unrouted Nets:                 1 out of    27
      Rejected Port Nets:                     8 out of    27
    Total guided:                            14 out of    27   51%

Guide file: "\example-8-1\modular_design\pims/module_b/module_b.ncd"       
Guide mode: "exact"

  Components:
    Name matched:                            10 out of    28   35%
    Total guided:                             7 out of    10   69%

  Signals:
    LOGIC0/LOGIC1 nets ignored:               2 out of    37
    Name matched:                            27 out of    35   77%
      Rejected Port Nets:                     7 out of    27
    Total guided:                             9 out of    27   33%

Guide file: "\example-8-1\modular_design\pims/module_c/module_c.ncd"       
Guide mode: "exact"

  Components:
    Name matched:                            11 out of    29   37%
    Total guided:                             8 out of    11   72%

  Signals:
    LOGIC0/LOGIC1 nets ignored:               2 out of    39
    Name matched:                            28 out of    37   75%
      Rejected Unrouted Nets:                 1 out of    28
      Rejected Port Nets:                     7 out of    28
    Total guided:                             9 out of    28   32%

================================================================================
Guide Detail Report:
================================================================================
================================================================================
For Guide file: "\example-8-1\modular_design\pims/module_a/module_a.ncd"

Components:
  Guided components meeting matching criteria:
    * Comp a2c (a2c) guided to site SLICE_X2Y13.
    * Comp a2top_obuft_i (a2top_obuft_i) guided to site SLICE_X2Y12.
    * Comp moda_out (moda_out) guided to site D5.
    * Comp moda_data (moda_data) guided to site A5.
    * Comp instance_a/MODA_OUT (instance_a/MODA_OUT) guided to site SLICE_X3Y14.
    * Comp instance_a/Q0_OUT (instance_a/Q0_OUT) guided to site SLICE_X2Y14.
    * Comp instance_a/Q1_OUT (instance_a/Q1_OUT) guided to site SLICE_X3Y12.
    * Comp instance_a/Q2_OUT (instance_a/Q2_OUT) guided to site SLICE_X3Y15.
    * Comp instance_a/Q3_OUT (instance_a/Q3_OUT) guided to site SLICE_X2Y11.
    * Comp a2b (a2b) guided to site SLICE_X2Y10.


Signals:
  Port Nets ignored:
    Name matched in guide file and design, but
        rejected due to being a Port Net:
    * moda_clk
    * a2c
    * clk_top
    * b2a
    * a2top_obuft_i
    * top2a_c_c
    * c2a
    * a2b

  Guided signals meeting matching criteria:
    * Sig instance_a/Q3_OUT (instance_a/Q3_OUT) guided.
    * Sig instance_a/Q0_OUT (instance_a/Q0_OUT) guided.
    * Sig instance_a/Q1_OUT (instance_a/Q1_OUT) guided.
    * Sig instance_a/Q2_OUT (instance_a/Q2_OUT) guided.
    * Sig instance_a/N_11_i (instance_a/N_11_i) guided.
    * Sig instance_a/G_7 (instance_a/G_7) guided.
    * Sig bufg_modb/IBUFG (bufg_modb/IBUFG) guided.
    * Sig dll_rst_c (dll_rst_c) guided.
    * Sig instance_a/MODA_OUT (instance_a/MODA_OUT) guided.
    * Sig dll_clk_in (dll_clk_in) guided.
    * Sig bufg_moda/IBUFG (bufg_moda/IBUFG) guided.
    * Sig bufg_modc/IBUFG (bufg_modc/IBUFG) guided.
    * Sig instance_a/MODA_DATA (instance_a/MODA_DATA) guided.
    * Sig dll_clk_out (dll_clk_out) guided.


================================================================================
For Guide file: "\example-8-1\modular_design\pims/module_b/module_b.ncd"

Components:
  Guided components meeting matching criteria:
    * Comp b2a (b2a) guided to site SLICE_X8Y14.
    * Comp modb_data (modb_data) guided to site C6.
    * Comp top2b (top2b) guided to site A6.
    * Comp modb_out (modb_out) guided to site B6.
    * Comp b2c (b2c) guided to site SLICE_X9Y13.
    * Comp instance_b/Q0_OUT (instance_b/Q0_OUT) guided to site SLICE_X9Y15.
    * Comp b2top_obuft_t (b2top_obuft_t) guided to site SLICE_X8Y13.
    * Comp instance_b/Q1_OUT (instance_b/Q1_OUT) guided to site SLICE_X9Y12.
    * Comp instance_b/Q2_OUT (instance_b/Q2_OUT) guided to site SLICE_X8Y15.
    * Comp instance_b/Q3_OUT (instance_b/Q3_OUT) guided to site SLICE_X8Y12.


Signals:
  Port Nets ignored:
    Name matched in guide file and design, but
        rejected due to being a Port Net:
    * clk_top
    * b2a
    * b2top_obuft_t
    * modb_clk
    * b2c
    * a2b
    * a_and_c

  Guided signals meeting matching criteria:
    * Sig instance_b/Q0_OUT (instance_b/Q0_OUT) guided.
    * Sig instance_b/Q1_OUT (instance_b/Q1_OUT) guided.
    * Sig instance_b/Q2_OUT (instance_b/Q2_OUT) guided.
    * Sig instance_b/Q3_OUT (instance_b/Q3_OUT) guided.
    * Sig instance_b/AND4_OUT (instance_b/AND4_OUT) guided.
    * Sig instance_b/OR4_OUT (instance_b/OR4_OUT) guided.
    * Sig instance_b/MODB_OUT (instance_b/MODB_OUT) guided.
    * Sig instance_b/MODB_DATA (instance_b/MODB_DATA) guided.
    * Sig instance_b/TOP2B_IN (instance_b/TOP2B_IN) guided.


================================================================================
For Guide file: "\example-8-1\modular_design\pims/module_c/module_c.ncd"

Components:
  Guided components meeting matching criteria:
    * Comp instance_c/C2TOP_OUT (instance_c/C2TOP_OUT) guided to site
SLICE_X4Y12.
    * Comp c2and2 (c2and2) guided to site SLICE_X4Y13.
    * Comp mod_c_out (mod_c_out) guided to site C8.
    * Comp modc_out (modc_out) guided to site B8.
    * Comp modc_data (modc_data) guided to site A8.
    * Comp instance_c/Q0_OUT (instance_c/Q0_OUT) guided to site SLICE_X4Y15.
    * Comp instance_c/Q2_OUT (instance_c/Q2_OUT) guided to site SLICE_X5Y15.
    * Comp c2a (c2a) guided to site SLICE_X4Y10.
    * Comp instance_c/Q1_OUT (instance_c/Q1_OUT) guided to site SLICE_X5Y12.
    * Comp instance_c/Q3_OUT (instance_c/Q3_OUT) guided to site SLICE_X5Y13.
    * Comp instance_c/MODC_OUT (instance_c/MODC_OUT) guided to site SLICE_X4Y14.


Signals:
  Port Nets ignored:
    Name matched in guide file and design, but
        rejected due to being a Port Net:
    * a2c
    * clk_top
    * modc_clk
    * c2and2
    * top2a_c_c
    * b2c
    * c2a

  Guided signals meeting matching criteria:
    * Sig instance_c/Q0_OUT (instance_c/Q0_OUT) guided.
    * Sig instance_c/Q1_OUT (instance_c/Q1_OUT) guided.
    * Sig instance_c/Q2_OUT (instance_c/Q2_OUT) guided.
    * Sig instance_c/Q3_OUT (instance_c/Q3_OUT) guided.
    * Sig instance_c/OR4_OUT (instance_c/OR4_OUT) guided.
    * Sig instance_c/C2TOP_OUT (instance_c/C2TOP_OUT) guided.
    * Sig instance_c/AND4_OUT (instance_c/AND4_OUT) guided.
    * Sig instance_c/MODC_OUT (instance_c/MODC_OUT) guided.
    * Sig instance_c/MODC_DATA (instance_c/MODC_DATA) guided.