top.srr

学习Xilinx公司开发软件ISE的基础资料

$ Start of Compile
#Wed Mar 26 20:44:19 2003

Synplicity Verilog Compiler, version 7.2, Build 112R, built Oct 23 2002
Copyright (C) 1994-2002, Synplicity Inc.  All Rights Reserved

@I::"J:\Example-8-1\Modular_Design\syn_top\virtex2.v"
@I::"J:\Example-8-1\Modular_Design\syn_top\top.v"
Verilog syntax check successful!
Selecting top level module top
Synthesizing module IBUFG
Synthesizing module CLKDLL
Synthesizing module BUFG
Synthesizing module BUFGP
Synthesizing module module_a
@W:"J:\Example-8-1\Modular_Design\syn_top\top.v":86:7:86:14|Creating black box for empty module module_a

Synthesizing module module_b
@W:"J:\Example-8-1\Modular_Design\syn_top\top.v":100:7:100:14|Creating black box for empty module module_b

Synthesizing module module_c
@W:"J:\Example-8-1\Modular_Design\syn_top\top.v":114:7:114:14|Creating black box for empty module module_c

Synthesizing module top
@END
Process took 0.0999999 seconds realtime, 0.1 seconds cputime
Synplicity Xilinx Technology Mapper, version 7.2, Build 175R, built Oct 24 2002
Copyright (C) 1994-2002, Synplicity Inc.  All Rights Reserved


Found 4 global buffers instantiated by user
Net buffering Report for view:work.top(verilog):
No nets needed buffering.

@N|The option to pack flops in the IOB has not been specified 
Writing Analyst data base J:\Example-8-1\Modular_Design\syn_top\rev_1\top.srm
Writing EDIF Netlist and constraint files
@W:"j:\example-8-1\modular_design\syn_top\top.v":73:9:73:18|Blackbox <module_c> is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
@W:"j:\example-8-1\modular_design\syn_top\top.v":63:9:63:18|Blackbox <module_b> is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
@W:"j:\example-8-1\modular_design\syn_top\top.v":53:9:53:18|Blackbox <module_a> is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 


##### START TIMING REPORT #####
# Timing Report written on Wed Mar 26 20:44:21 2003
#


Top view:              top
Paths requested:       5
Constraint File(s):    
@N| This timing report estimates place and route data. Please look at the place and route timing report for final timing.
@N| Clock constraints cover all FF-to-FF, FF-to-output, input-to-FF and input-to-output paths associated with a particular clock.



Performance Summary 
*******************


Worst slack in design: 994.509

                   Requested     Estimated     Requested     Estimated                 Clock 
Starting Clock     Frequency     Frequency     Period        Period        Slack       Type  
---------------------------------------------------------------------------------------------
System             1.0 MHz       182.1 MHz     1000.000      5.491         994.509     system
=============================================================================================



Interface Information 
*********************



Input Ports: 

Port                Starting            User           Arrival     Required            
Name                Reference           Constraint     Time        Time         Slack  
                    Clock                                                              
---------------------------------------------------------------------------------------
dll_rst             NA                  NA             NA          NA           NA     
ipad_dll_clk_in     System (rising)     NA             0.000       998.976      998.976
moda_clk_pad        System (rising)     NA             0.000       998.770      998.770
moda_data           System (rising)     NA             0.000       998.742      998.742
modb_clk_pad        System (rising)     NA             0.000       998.770      998.770
modb_data           System (rising)     NA             0.000       998.742      998.742
modc_clk_pad        System (rising)     NA             0.000       998.770      998.770
modc_data           System (rising)     NA             0.000       998.742      998.742
top2a_c             System (rising)     NA             0.000       998.678      998.678
top2b               System (rising)     NA             0.000       998.742      998.742
=======================================================================================


Output Ports: 

Port          Starting            User           Arrival     Required            
Name          Reference           Constraint     Time        Time         Slack  
              Clock                                                              
---------------------------------------------------------------------------------
mod_c_out     System (rising)     NA             5.491       1000.000     994.509
moda_out      System (rising)     NA             5.491       1000.000     994.509
modb_out      System (rising)     NA             5.491       1000.000     994.509
modc_out      System (rising)     NA             5.491       1000.000     994.509
obuft_out     System (rising)     NA             5.491       1000.000     994.509
=================================================================================



====================================
Detailed Report for Clock: System
====================================



Starting Points with worst slack 
********************************

                                                                    Arrival            
Instance       Type         Pin                   Net               Time        Slack  
                                                                                       
---------------------------------------------------------------------------------------
instance_a     module_a     A2TOP_OBUFT_I_OUT     a2top_obuft_i     0.000       994.509
instance_a     module_a     MODA_OUT              moda_out_c        0.000       994.509
instance_b     module_b     MODB_OUT              modb_out_c        0.000       994.509
instance_c     module_c     C2TOP_OUT             mod_c_out_c       0.000       994.509
instance_c     module_c     MODC_OUT              modc_out_c        0.000       994.509
instance_b     module_b     B2TOP_OBUFT_T_OUT     b2top_obuft_t     0.000       994.569
top2a_c        Port         top2a_c               top2a_c           0.000       998.678
moda_data      Port         moda_data             moda_data         0.000       998.742
modb_data      Port         modb_data             modb_data         0.000       998.742
modc_data      Port         modc_data             modc_data         0.000       998.742
=======================================================================================


Ending Points with worst slack 
******************************

                                                           Required            
Instance       Type         Pin            Net             Time         Slack  
                                                                               
-------------------------------------------------------------------------------
mod_c_out      Port         mod_c_out      mod_c_out       1000.000     994.509
moda_out       Port         moda_out       moda_out        1000.000     994.509
modb_out       Port         modb_out       modb_out        1000.000     994.509
modc_out       Port         modc_out       modc_out        1000.000     994.509
obuft_out      Port         obuft_out      obuft_out       1000.000     994.509
instance_a     module_a     TOP2A_IN       top2a_c_c       1000.000     998.678
instance_c     module_c     TOP2A_C_IN     top2a_c_c       1000.000     998.678
instance_a     module_a     MODA_DATA      moda_data_c     1000.000     998.742
instance_b     module_b     MODB_DATA      modb_data_c     1000.000     998.742
instance_b     module_b     TOP2B_IN       top2b_c         1000.000     998.742
===============================================================================



Worst Paths Information
***********************


Path information for path number 1: 
    = Required time:                      1000.000

    - Propagation  time:                  5.491
    = Slack (critical) :                  994.509

    Starting point:                       instance_a / A2TOP_OBUFT_I_OUT
    Ending point:                         obuft_out / obuft_out
    The start point is clocked by         System [rising]
    The end   point is clocked by         System [rising]

Instance / Net                   Pin                   Pin               Arrival     Fan
Name                Type         Name                  Dir     Delay     Time        Out
----------------------------------------------------------------------------------------
instance_a          module_a     A2TOP_OBUFT_I_OUT     Out     0.000     0.000          
a2top_obuft_i       Net                                                              1  
obuft_out_obuft     OBUFT        I                     In                0.000          
obuft_out_obuft     OBUFT        O                     Out     5.491     5.491          
obuft_out           Net                                                              1  
obuft_out           Port         obuft_out             Out               5.491          
========================================================================================




##### END TIMING REPORT #####

---------------------------------------
Resource Usage Report for top 

Mapping to part: xc2v40cs144-5
Cell usage:
CLKDLL          1 use
module_a        1 use
module_b        1 use
module_c        1 use

I/O primitives:
IBUF           6 uses
IBUFG          1 use
OBUF           4 uses
OBUFT          1 use

BUFG           1 use

BUFGP          3 uses

I/O Register bits:                  0
Register bits not including I/Os:   0 (0%)

Global Clock Buffers: 4 of 16 (25%)


Mapping Summary:
Total  LUTs: 1 (0%)

Mapper successful!
Process took 1.623 seconds realtime, 1.622 seconds cputime